Datasheet

9-Feb-2022

CFR0011-120-01

Revision 1.04

Page 4 of 9

SLG55022-200030

High Voltage Gate Driver

©2022 Renesas Electronics Corporation

Device Operation

In a typical application, de-asserting ON (low) turns off the external power N-FET. When the FET is turned off, the voltage at the

load is discharged through a resistor (300 Ohms) internal to the SLG55022. When ON is asserted (high), the device will not begin

driving the gate of the external power FET unless the voltage at the drain of the device is at or above 0.8 V (e.g. VD ≥ 0.8 V) to

prevent a ‘shootthrough’ situation to the FET’s source load. Gate voltage is not applied to the gate of the external power N-FET

after DLY_t then the gate source (Vgs) voltage is ramped up to 11.5V above the source voltage VS at a slew rate determined by

the internal slew rate control element internal to the SLG55022. Monotonic rise of Vs is maintained even as ID increases

dramatically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum

steady state value, the Open Drain PG (Power Good) signal is asserted. PG may be used as the ON control of a second

SLG55022 thereby providing power on sequence control of a number of switched power rails, or used in a ‘wired and’ with other

PG signals to indicate all switched power rails are in a power good condition.

The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate

for variations in load current as the voltage is applied.