Datasheet

9-Feb-2022

CFR0011-120-01

Revision 1.04

Page 3 of 9

SLG55022-200030

High Voltage Gate Driver

©2022 Renesas Electronics Corporation

Absolute Maximum Ratings

Parameter

Min.

Max.

Unit

VD or VS to GND

-0.3

40.0

V

Voltage at Logic Input pins

-0.3

6.5

V

Current at input pin

-1.0

1.0

mA

Storage temperature range

-65

150

°C

Junction temperature

--

150

°C

ESD Human Body Model

--

2000

V

ESD Machine Model

--

200

V

Moisture Sensitivity Level

1

Electrical Characteristics

TA = -10 °C to 75 °C

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

VCC

Supply Voltage

11.5

12.0

12.5

V

TVCC_RAMP VCC Ramp-up Rate

See Note 1

0.25

--

--

V/ms

Iq

Quiescent Current

VG not ramping

FET = ON

50

80

µA

VG not ramping

FET = OFF

0.1

1

µA

VD

FET Drain Voltage

1.0

--

21

V

VGS

Gate-Source Voltage

8.0

11.5

16

V

CG

FET Gate Capacitance

500

--

8000

pF

TDELAY

Ramp Delay Range

1.5ms Default, 500

µs step

0

500

750

µs

TSLEW

FET Turn on Slew Rate

1.2

2.0

2.8

V/ms

IDISCHARGE Internal Discharge Resistor

Nominal discharge time of ~100ms

10mA max rate

180

300

420

Ω

VIH

HIGH-level input voltage

ON (200mV Hysteresis)

2.4

--

5.5

V

VIL

LOW-level Input voltage

ON (200mV Hysteresis)

--

--

0.4

V

VOH

HIGH-level output voltage

PG Open Drain

--

--

5.5

V

IOL_LOGIC

Logic LOW level output

PG Sink Current

1

2

3

mA

IIH

*

HIGH-level input current

VIH = 3.3V

--

--

<1.0

µA

Notes:

1. If TVCC_RAMP > 5V/ms and ON is asserted, Gate charging will begin after 1ms.