AND8020D datasheet(3/18 Pages) AD

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AND8020/D

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Output Open, Short, and Safe DC Current

Left open, an output will only swing a few millivolts due

to parasitic “minimum current” leakage paths.

Shorted to VEE, a maximum current will develop, limited

only by the output transistor 8

W impedance, and may cause

damage to the output. Worst case short circuit current risks

destruction of the devices.

ISC +

VOH

RINT

+ 4V

= 500 mA!

(eq. 1)

Where:

VOH = 4.0 V

VCC = 5.0 V

VEE = 0.0 V

Rint =8

The continuous safe output current, Iout (continuous),

maximum limit is 50 mA under all spec operating

conditions. The continuous safe repetitive surge, Iout

(surge),

maximum

current

limit

100

for

10 milliseconds per second duty cycle, provided the device’s

total thermal limits are observed. Output current polarity

will always be sinking into the termination scheme during

proper operation.

Static Analysis of Termination Resistor RE

The output continuous safe current limit, Iout (cont),

determines RE minimum DC termination scheme resistance

to VEE although this will not provide a practical AC signal

termination as shown in Table A: Minimum RE Values.

RE +

VOH

I max

(eq. 2)

Table A. Minimum RE Values

Line

VOH

RE(min)

PECL

4.0 V

LVPECL

2.4 V

LVEP PECL

1.6 V

A DC terminating resistor minimum, RE (min), of 80

while sufficiently limiting the output load current to VEE,

may generate insufficient PECL output LOW and HIGH

state transitions.

The RE maximum is effectively determined by the

application load capacitance, CL, since an RC network is

formed by RE and CL which limits the signal fall time,

discharging the line to the LOW state voltage level. A

sufficiently high value RE or CL can cause the signal fall

time to the VOL level to violate specification limits.

Designed RE or CL values may selectively eliminate

undesirable noise.

Dynamic Analysis of Termination Resistor RE

The dynamic function of the termination resistor, RE is to

develop the voltage change,

DV, during a high−to−low or

low−to−high transition and present this to the transmission

medium such as coax, twisted pair, microstrip or stripline.

The

DV signal propagates to the receiver and is either

reflected, dissipated, or a combination.

Since the reflection coefficient at the load is of opposite

polarity to that of the source, a reflection will travel back and

forth over the transmission changing polarity after each

reflection until critically damped by line impedance. Thus,

steps may appear in the signal

DV at the receiving gate input

due to impedance mismatch and consequent partial

reflections.

When RE is too large, steps appear in the trailing edge of

the propagating signal,

DV, at the input to the receiving gate,

slowing the edge speed and increasing the net propagation

delay. A reasonable negative−going signal swing at the input

of the receiving gate results when the value of RE is selected

to produce an initial step of 75% of the expected

DV, or a

600 mV step for an 800 mV signal at the driving gate. For

a RSECL expected

DV swing of 400, a 300 mV initial step

is desired. Hence for a 600 mV initial step:

(VOH * VEE )

(Rt ) Z0 )

*Z0 y 0.6

I(init) * Z0 u 0.6

(eq. 3)

The value for RE is found in Table B: Recommended

Values of RE in Dynamic Functional Application. This table

lists recommended RE values for the various ECL devices by

Family Series according to the equation above. The table

assumes operation with various data sheet VOH values and

various VCC values driving a Z0 = 50

W line. Lowering the

value of RE will increase the voltage change,

DV, launched

into the transmission media. Raising the value of RE will

decrease the voltage change,

DV, launched into the

transmission media.

Table B. Recommended Nominal Values of RE in

Dynamic Functional Application

Series

|VCC−VEE|

RE (W)

2.5

140

3.3

250

10/100LVEP

2.5

10/100EP, 100LVEL

3.3

120

10/100EL, 10/100E

5.0

235

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