AND8020/D

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18

Combining the high impedance and impedance matching

networks results in an input voltage scheme shown in

Figure 24. This creates the proper input voltage

D, VBIAS,

using fewer components.

Figure 24. VBIAS and Auto−Oscillation Suppression

with Thevenin Parallel Network

R1

Receiver

OUT

OUTb

IN

0.001

mF

R2

INb

0.001

mF

R1

+ 4.22 kW

R2

+ 6.34 kW

RZ + 100 W

The 0.001 coupling cap may need to be adjusted to

frequency and Vpp amplitude of the receiver input signal.

A similar single−ended network may be used with only

one coupling cap and sufficient bypass capacitance on the

non−driven resistor to preserve a DC level.

Output Level Shifting

Receiver inputs may be level shifted using capacitive

coupling and adjusting VBIAS within the acceptable

changed independent of input levels. The driver device may

is used at the factory to evaluate devices and conveniently

port signals directly into standard 50

W impedance

System chassis ground and the test equipment internal 50

W

impedance constitutes a proper signal termination. Thus, the

Unit

3.0

+2.0

−1.0

V

3.3

+2.0

−1.3

V

5.0

+2.0

−3.0

V

5.5

+2.0

−3.5

V

Output levels may be shifted to symmetrically cross 0.0 V

by a similar method although the advantage of conveniently

directly connecting into standard test equipment is no longer

available.

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