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AND8020D датащи(PDF) 1 Page - Analog Devices |
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AND8020D датащи(HTML) 1 Page - Analog Devices |
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1 / 18 page ![]() © Semiconductor Components Industries, LLC, 2004 July, 2004 − Rev. 5 1 Publication Order Number: AND8020/D AND8020/D Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering CONTENTS OF APPLICATION NOTE Introduction − DC Termination Analysis Vt Rt Rt Rt Rt Rt Rt Vt1 Vt2 External Internal Near (Standard Pair) Far (Standard Pair) Far (Standard Pair) VEE Rt Rt Rt Rt Rt Vt1 Vt2 VEE Vto (Open) VEE (Shorted) VTT Near (Standard Pair) VTT VTT RE VEE Section 2. Parallel Termination − External and Internal Section 1. Unterminated Lines R R R R Section 3. Thevenin Equivalent/Parallel Termination R R Section 4. Series (Back) Termination VBB VBB Driver Receiver *All Media * * D1 D2 D1 D2 Section 5. Diode Termination R R R R R VCC VBB Section 6. Capacitive Coupling RE RE RE RE RE RE RE RE APPLICATION NOTE http://onsemi.com |
Аналогичный номер детали - AND8020D |
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Аналогичное описание - AND8020D |
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