S12SCIV3SLASHD datasheet(45/98 Pages) NXP

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MC9S12KG128 SoC Guide — V01.01

execution, the system will be configured as described below unless the reset states of internal control

registers have been changed through background commands after the MCU was reset.

There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional

I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to

the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.

All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance

inputs with pull-ups enabled. PE4/ECLK is configured as the ECLK output in this mode.

The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,

IPIPE0, LSTRB, and R/W while the MCU is in single chip modes In single chip modes, the associated

control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in

single chip mode does not change the operation of the associated Port E pins.

Port E, bit 4 can be configured for a free-running ECLK output by clearing NECLK=0. Typically the only

use for an ECLK output while the MCU is in single chip modes would be to get a constant speed clock for

use in the external application system.

4.2.2.2 Special Test Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and

Port E provides bus control and status signals. In special test mode, the write protection of many control

bits is lifted so that they can be thoroughly tested without needing to go through reset.

4.2.2.3 Special Peripheral Mode

This mode is intended for Freescale factory testing of the MCU. In this mode, the CPU is inactive and an

external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In

effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster

testing of on-chip memory and peripherals than previous testing methods. Since the mode control register

is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a

different mode. Background debugging should not be used while the MCU is in special peripheral mode

as internal bus conflicts between BDM and the external master can cause improper operation of both

functions.

4.3 Internal Visibility

Internal visibility is available when the MCU is operating in expanded wide modes or special test modes.

It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is

enabled by setting the IVIS bit in the MODE register.

If an internal access is made while the ECLK, R/W, and LSTRB are configured as bus control outputs and

internal visibility is off (IVIS=0), ECLK will remain low for the cycle, R/W will remain high, and address,

data and the LSTRB pins will remain at their previous state.

When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external.

During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and

address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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