S12SCIV3SLASHD datasheet(32/98 Pages) NXP

номер детали	S12SCIV3/D

подробное описание детали	The SoC Guide provides information about the MC9S12KG128 device made up of standard HCS12 blocks and the HCS12 processor core

PDF	98 Pages

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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MC9S12KG128 SoC Guide — V01.01

Figure 2-6 External Clock Connections (XCLKS=0)

2.3.11 PE6 / MODB / IPIPE1 — Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.

The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the

instruction queue tracking signal IPIPE1.

2.3.12 PE5 / MODA / IPIPE0 — Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.

The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the

instruction queue tracking signal IPIPE0.

2.3.13 PE4 / ECLK — Port E I/O Pin 4

PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.

ECLK can be used as a timing reference.

2.3.14 PE3 / LSTRB / TAGLO — Port E I/O Pin 3

PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used

for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,

TAGLO is used to tag the low half of the instruction word being read into the instruction queue.

2.3.15 PE2 / R/W — Port E I/O Pin 2

PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the

read/write output signal for the external bus. It indicates the direction of data on the external bus.

MCU

EXTAL

XTAL

CMOS-COMPATIBLE

EXTERNAL OSCILLATOR

not connected

(VDDPLL-Level)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

S12SCIV3/D датащи(PDF) 32 Page - NXP Semiconductors