REVISION 9 3/15/16

2

©2016 Integrated Device Technology, Inc.

MPC9447 DATA SHEET

Figure 1. Logic Diagram

Figure 2. 32-Lead Pinout (Top View)

0

1

CCLK0

CCLK1

CLK_SEL

CLK_STOP

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

VCC

VCC

25k

VCC

25k

VCC

CLK

Stop

SYNC

(All input resistors have a value of 25 k

)

GND

Q2

VCC

Q1

GND

Q0

VCC

GND

Q6

VCC

Q7

GND

Q8

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

3

4

5

6

78

24

23

22

21

20

19

18

17

16

MPC9447

GND

VCC

GND

Table 1. Function Table

Control

Default

0

1

CLK_SEL

1

CLK0 input selected

CLK1 input selected

OE

1

Outputs disabled (high-impedance state)(1)

1. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP.

Outputs enabled

CLK_STOP

1

Outputs synchronously stopped in logic low state

Outputs active

Table 2. Pin Configurations

Pin

I/O

Type

Function

CCLK0

Input

LVCMOS

Clock Signal Input

CCLK1

Input

LVCMOS

Alternative Clock Signal Input

CLK_SEL

Input

LVCMOS

Clock Input Select

CLK_STOP

Input

LVCMOS

Clock Output Enable/Disable

OE

Input

LVCMOS

Output Enable/Disable (high-impedance tristate)

Q0–8

Output

LVCMOS

Clock Outputs

GND

Supply

Ground

Negative Power Supply (GND)

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be connected to the

positive power supply for correct operation