REVISION 9 3/15/16

7

3.3V, 2.5V, 1:9 LVCMOS CLOCK FANOUT BUFFER

MPC9447 DATA SHEET

Since this step is well above the threshold region, it will not cause

any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better match

the impedances when driving multiple lines, the situation in Figure 6

should be used. In this case, the series terminating resistors are

reduced such that when the parallel combination is added to the

output buffer impedance, the line impedance is perfectly matched.

Figure 6. Optimized Dual Line Termination

The Following Figures Illustrate the Measurement Reference for the MPC9447 Clock Driver Circuit

Figure 7. CCLK MPC9447 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V

17



MPC9447

Output

Buffer

RS = 16

ZO = 50

RS = 16

ZO = 50

17

+ 16 || 16 = 50 || 50

25

 = 25

Pulse

Generator

Z = 50



RT = 50

ZO = 50

RT = 50

ZO = 50

MPC9447 DUT

VTT

VTT