REVISION 9 3/15/16

8

©2016 Integrated Device Technology, Inc.

MPC9447 DATA SHEET

Figure 8. Propagation Delay (tPD) Test Reference

Figure 9. Output-to-Output Skew tSK(LH, HL)

Figure 10. Output Pulse Skew (tSK(P)) Test Reference

Figure 11. Output Duty Cycle (DC)

Figure 12. Output Transition Time Test Reference

Figure 13. Cycle-to-Cycle Jitter

Figure 14. Setup and Hold Time (tS, tH) Test Reference

VCC

VCC2

GND

VCC

VCC2

GND

CCLK

QX

tP(LH)

tP(HL)

The pin-to-pin skew is defined as the worst case difference in

propagation delay between any similar delay path within a single

device.

VCC

VCC2

GND

VCC

VCC2

GND

tSK(LH)

tSK(HL)

VCC

VCC2

GND

VCC

VCC2

GND

tP(LH)

CCLK

QX

tP(HL)

tSK(P) = | tPLH – tPHL |

The time from the output controlled edge to the non-controlled edge,

divided by the time between output controlled edges, expressed as

a percentage.

VCC

VCC2

GND

tP

T0

DC = (tP ? T0 x 100%)

tF

tR

VCC=3.3 V VCC=2.5 V

2.4

1.8 V

0.55

0.6 V

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs.

TN

TJIT(CC) = |TN-TN+1|

TN+1

VCC

VCC2

GND

VCC

VCC2

GND

tS

CCLK

PCLK

CLK_STOP

tH