SN250 datasheet(118/130 Pages) STMICROELECTRONICS

118 / 130 page

Typical application

SN250

118/130

Typical application

Figure 16 illustrates the typical application circuit for the SN250. This figure does not contain

all decoupling capacitance required by the SN250. The Balun provides the impedance

transformation from the antenna to the SN250 for both TX and RX modes. The harmonic

filter provides additional suppression of the second harmonic, which increases the margin

over the FCC limit. The 24MHz crystal with loading capacitors is required and provides the

high frequency source for the SN250. The 32.768kHz crystal generates the clock source for

the Sleep Timer, but it is not mandatory as the internal RC Oscillator can be used. The RC

debounce filter (R4 and C9) is suggested to improve the noise immunity of the RESET logic

(pin 13).

Figure 16.

Typical application circuit

Table 39 contains the bill of materials for the application circuit shown in Figure 16.

Optional

VDD_24MHZ

VDD_VCO

RF_N

RF_P

VDD_RF

RF_TX_ALT_P

RF_TX_ALT_N

VDD_IF

BIAS_R

VDD_PADSA

TX_ACTIVE

SIF_MOSI

SIF_MISO

SIF_CLK

GPIO10, RXD, MI, MSCL, TMR1IB.2

GPIO9, TXD, MO, MSDA, TMR1IA.2

GPIO8, VREF, TMR1CLK, TMR2ENMSK, IRQA

GPIO7, ADC3, REG_EN

GPIO6, ADC2, TMR2CLK,TMR1ENMSK

VDD_PADS

GPIO5, ADC1, PTI_DATA

GPIO4, ADC0, PTI_EN

GPIO3, nSSEL, TMR1IB.1

VDD_PADSA

GND

SN250

Ceramic

Balun (BLN1)

1.8V

VDD_PADS

(2.1V to 3.6V)

Programming and

Debug Interface (these

pins should be routed

to test points)

Harmonic

Filter

VDD_PADS

(2.1V to 3.6V)

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