 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
P89C51RB2BA датащи(PDF) 33 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P89C51RB2BA датащи(HTML) 33 Page - NXP Semiconductors |
|
|
33 / 52 page  Philips Semiconductors Preliminary specification 89C51RB2/89C51RC2/ 89C51RD2 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM 1999 Sep 23 33 AC ELECTRICAL CHARACTERISTICS (6 CLOCK MODE) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK4 20 MHz CLOCK4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 29 Oscillator frequency 0 20 0 20 MHz tLHLL 29 ALE pulse width tCLCL–40 10 ns tAVLL 29 Address valid to ALE low 0.5tCLCL–20 5 ns tLLAX 29 Address hold after ALE low 0.5tCLCL–20 5 ns tLLIV 29 ALE low to valid instruction in 2tCLCL–65 35 ns tLLPL 29 ALE low to PSEN low 0.5tCLCL–20 5 ns tPLPH 29 PSEN pulse width 1.5tCLCL–45 30 ns tPLIV 29 PSEN low to valid instruction in 1.5tCLCL–60 15 ns tPXIX 29 Input instruction hold after PSEN 0 0 ns tPXIZ 29 Input instruction float after PSEN 0.5tCLCL–20 5 ns tAVIV 29 Address to valid instruction in 2.5tCLCL–80 45 ns tPLAZ 29 PSEN low to address float 10 10 ns Data Memory tRLRH 30, 31 RD pulse width 3tCLCL–100 50 ns tWLWH 30, 31 WR pulse width 3tCLCL–100 50 ns tRLDV 30, 31 RD low to valid data in 2.5tCLCL–90 35 ns tRHDX 30, 31 Data hold after RD 0 0 ns tRHDZ 30, 31 Data float after RD tCLCL–20 5 ns tLLDV 30, 31 ALE low to valid data in 4tCLCL–150 50 ns tAVDV 30, 31 Address to valid data in 4.5tCLCL–165 60 ns tLLWL 30, 31 ALE low to RD or WR low 1.5tCLCL–50 1.5tCLCL+50 25 125 ns tAVWL 30, 31 Address valid to WR low or RD low 2tCLCL–75 25 ns tQVWX 30, 31 Data valid to WR transition 0.5tCLCL–25 0 ns tWHQX 30, 31 Data hold after WR 0.5tCLCL–20 5 ns tQVWH 31 Data valid to WR high 3.5tCLCL–130 45 ns tRLAZ 30, 31 RD low to address float 0 0 ns tWHLH 30, 31 RD or WR high to ALE high 0.5tCLCL–20 0.5tCLCL+20 5 45 ns External Clock tCHCX 33 High time 20 tCLCL–tCLCX ns tCLCX 33 Low time 20 tCLCL–tCHCX ns tCLCH 33 Rise time 5 ns tCHCL 33 Fall time 5 ns Shift Register tXLXL 32 Serial port clock cycle time 6tCLCL 300 ns tQVXH 32 Output data setup to clock rising edge 5tCLCL–133 117 ns tXHQX 32 Output data hold after clock rising edge tCLCL–30 20 ns tXHDX 32 Input data hold after clock rising edge 0 0 ns tXHDV 32 Clock rising edge to input data valid 5tCLCL–133 117 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
