Philips Semiconductors

Preliminary specification

89C51RB2/89C51RC2/

89C51RD2

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/512B/1KB RAM

1999 Sep 23

31

ERAM

256 or 768 BYTES

UPPER

128 BYTES

INTERNAL RAM

LOWER

128 BYTES

INTERNAL RAM

SPECIAL

FUNCTION

REGISTER

100

FF

00

FF

00

80

80

EXTERNAL

DATA

MEMORY

FFFF

0000

SU01293

Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0

HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR 89C51RB2/RC2/RD2)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit

counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, user must write 01EH and 0E1H in

sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and

there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an

output reset HIGH pulse at the RST-pin (see the note below).

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to

service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this

will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset

the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only

register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the reset pin (see note

below). The RESET pulse duration is 98

should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

PARAMETER

RATING

UNIT

Operating temperature under bias

0 to +70 or –40 to +85

°C

Storage temperature range

–65 to +150

°C

0 to +13.0

V

–0.5 to +6.5

V

15

mA

Power dissipation (based on package heat transfer limitations, not device power consumption)

1.5

W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

4. Programming is guaranteed from 0