P87LPC768FD datasheet(20/64 Pages) PHILIPS

20 / 64 page

Philips Semiconductors

Preliminary data

87LPC768

Low power, low price, low pin count (20 pin) microcontroller

with 4 kB OTP 8-bit A/D, Pulse Width Modulator

2001 Aug 06

state when Run is cleared the Compare registers can be written to

either the “always 1” or “always 0” so the output will have the output

desired when the counter is halted. After this PWMCON0 should be

written with the Transfer and Run bits are enabled. After this is

done PWMCON0 to is polled to find that the Transfer has taken

place. Once the transfer has occurred the Run bit in PWMCON0

can be cleared. The outputs will retain the state they had just prior

to the Run being cleared. If the Brake pin (see discussion below in

section concerning the operation of PWMCON1) is not used to

control the brake function, the “Brake when not running” function can

be used to cause the outputs to have a given state when the PWM

is halted. This approach should be used only in time critical

situations when there is not sufficient time to use the approach

outlined above since going from the Brake state to run without

causing an undefined state on the outputs is not straightforward. A

discussion on this topic is included in the section on PWMCON1.

PWMCON0: PWM Control register 0

Addr: 0DAH

Reset Value: 00H

BIT

SYMBOL

FUNCTION

PWMCON0.7

RUN

0= Counter Halted & Preset Value loaded. If Brake is asserted, PWMx output will be equal to the

value of the corresponding PWMxB bit (PWMCON1[3:0]). If Brake is not asserted, PWMx

output will be equal to the Value after compare

1= Counter run

PWMCON0.6

XFER

0= Counter & Compare shadow registers are not connected to the active registers

1= Shadow register contents transferred to active registers, at the next Counter underflow This bit

is auto–cleared by hardware after the data transfer from shadow to active registers

PWMCON0.5

PWM3I

0= PWM3 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’

thereafter.

1= PWM3 output is inverted. Output is a ‘0’ from the start of the cycle until compare; ’0’ thereafter.

PWMCON0.4

PWM2I

0= PWM2 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’

thereafter.

1= PWM2 output is inverted. Output is ‘0’ from the start of the cycle until compare; ’1’ thereafter.

PWMCON0.2

PWM1I

0= PWM1 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’

thereafter.

1= PWM1 output is inverted. Output is ‘0’ from the start of the cycle until compare; ’1’ thereafter.

PWMCON0.1

PWM0I

0= PWM0 output is non–inverted. Output is a ‘1’ from the start of the cycle until compare; ’0’

thereafter.

1= PWM0 output is inverted. Output is ‘0’ from the start of the cycle until compare; ’1’ thereafter.

RUN

XFER

PWM3I

PWM2I

–

PWM1I

PWM0I

–

SU01387

The Brake function, which is controlled by the contents of the

PWMCON1 register, is somewhat unique. In general when Brake is

asserted the four PWM outputs are forced to a user selected state,

namely the state selected by PWMCON1 bits 0 to 3.

As shown in the description of the operation of the PWMCON1

PWMCON1.7, BKCH, and PWMCON1.5, BPEN. As shown if both

are a “0” Brake is asserted. If PWMCON1.7 is a “1” brake is

asserted when the run bit, PWMCON0.7, is a “0.” If PWMCON1.6 is

a “1” brake is asserted when the Brake Pin, P0.2, has the same

polarity as PWMCON1.6. When brake is asserted in response to

this pin the RUN bit, PWMCON0.7, is automatically cleared. The

combination of both PWMCON1.7 and PWMCON1.5 being a “1” is

not allowed.

Since the Brake Pin being asserted will automatically clear the Run

bit, PWMCON0.7, the user program can poll this bit to determine

when the Brake Pin causes a brake to occur. The other method for

detecting a brake caused by the Brake Pin would be to tie the Brake

Pin to one of the external interrupt pins. This latter approach is

needed if the Brake signal can be of insufficient length to ensure

that it can be captured by a polling routine.

When, after being asserted, the condition causing the brake is

removed, the PWM outputs go to whatever state that had

immediately prior to the brake. This means that in order to go from

brake being asserted to having the PWM run without going through

an indeterminate state care must be taken. If the Brake Pin causes

brake to be asserted the following prototype code will allow the

PWM to go from brake to run smoothly.

• Rewrite PWMCON1 to change from Brake Pin enabled to S/W

Brake

• Write CPSW.(0:4) to always “1”, 11 h, or always “0” 00 h, to give

brake pattern

• Set PWMCON0 to enable Run and Transfer.

• Poll Brake Pin until it is no longer active. When no longer active:

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