P87LPC768FD datasheet(15/64 Pages) PHILIPS

15 / 64 page

Philips Semiconductors

Preliminary data

87LPC768

Low power, low price, low pin count (20 pin) microcontroller

with 4 kB OTP 8-bit A/D, Pulse Width Modulator

2001 Aug 06

Analog Comparators

Two analog comparators are provided on the 87LPC768. Input and

output options allow use of the comparators in a number of different

configurations. Comparator operation is such that the output is a

logical one (which may be read in a register and/or routed to a pin)

when the positive input (one of two selectable pins) is greater than

the negative input (selectable from a pin or an internal reference

voltage). Otherwise the output is a zero. Each comparator may be

configured to cause an interrupt when the output value changes.

Comparator Configuration

Each comparator has a control register, CMP1 for comparator 1 and

CMP2 for comparator 2. The control registers are identical and are

shown in Figure 4.

The overall connections to both comparators are shown in Figure 5.

There are eight possible configurations for each comparator, as

determined by the control bits in the corresponding CMPn register:

CPn, CNn, and OEn. These configurations are shown in Figure 6.

The comparators function down to a VDD of 3.0V.

When each comparator is first enabled, the comparator output and

interrupt flag are not guaranteed to be stable for 10 microseconds.

The corresponding comparator interrupt should not be enabled

during that time, and the comparator interrupt flag must be cleared

before the interrupt is enabled in order to prevent an immediate

interrupt service.

BIT

SYMBOL

FUNCTION

CMPn.7, 6

—

Reserved for future use. Should not be set to 1 by user programs.

CMPn.5

CEn

Comparator enable. When set by software, the corresponding comparator function is enabled.

Comparator output is stable 10 microseconds after CEn is first set.

CMPn.4

CPn

Comparator positive input select. When 0, CINnA is selected as the positive comparator input. When

1, CINnB is selected as the positive comparator input.

CMPn.3

CNn

Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as

the negative comparator input. When 1, the internal comparator reference Vref is selected as the

negative comparator input.

CMPn.2

OEn

Output enable. When 1, the comparator output is connected to the CMPn pin if the comparator is

enabled (CEn = 1). This output is asynchronous to the CPU clock.

CMPn.1

COn

Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the

comparator is disabled (CEn = 0).

CMPn.0

CMFn

Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes

state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by

software and when the comparator is disabled (CEn = 0).

CMFn

SU01152

COn

OEn

CNn

CPn

CEn

—

CMPn

Reset Value: 00h

Not Bit Addressable

Address: ACh for CMP1, ADh for CMP2

Figure 4. Comparator Control Registers (CMP1 and CMP2)

P87LPC768FD датащи(PDF) 15 Page - NXP Semiconductors

P87LPC768FD датащи(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

датащи скачать

ссылки URL