IDT80KSW0002

Datasheet

CPS-16 Datasheet

47

April 6, 2016

Table 21 Receiver AC Timing Specifications - 1.25 GBaud

NOTE:

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have

any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter,

wander, noise, crosstalk and other variable system effects.

Table 22 Receiver AC Timing Specifications - 2.5 GBaud

NOTE:

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have

any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component is included to ensure margin for low frequency jitter,

wander, noise, crosstalk and other variable system effects.

Symbol

Parameter

Range

Unit

Notes

Min

Max

VIN

Differential Input Voltage

200

1600

mV p-p

Measured at receiver

JD

Deterministic Jitter Tolerance

0.37

-

UI p-p

Measured at receiver

JDR

Combined Deterministic and

Random Jitter Tolerance

0.55

-

UI p-p

Measured at receiver

JT

Total Jitter Tolerance(1)

0.65

-

UI p-p

Measured at receiver

SMI

Multiple Input Skew

-

24

ns

Skew at the receiver input

between lanes of a multi-

lane link

BER

Bit Error Rate

10-12

UI

Unit Interval

800

800

ps

+/- 100 ppm

Symbol

Parameter

Range

Unit

Notes

Min

Max

VIN

Differential Input Voltage

200

1600

mV p-p

Measured at receiver

JD

Deterministic Jitter Tolerance

0.37

-

UI p-p

Measured at receiver

JDR

Combined Deterministic and

Random Jitter Tolerance

0.55

-

UI p-p

Measured at receiver

JT

Total Jitter Tolerance(1)

0.65

-

UI p-p

Measured at receiver

SMI

Multiple Input Skew

-

24

ns

Skew at the receiver input

between lanes of a multi-

lane link

BER

Bit Error Rate

10-12

UI

Unit Interval

400

400

ps

+/- 100 ppm