IDT80KSW0002

Datasheet

CPS-16 Datasheet

47

April 6, 2016

I2C AC Electrical Specifications

Table 11 Specifications of the SDA and SCL bus lines for F/S-mode I2C -bus devices

NOTES:

1. For more information, see the I2C-Bus specification by Philips Semiconductor [1].

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the unde-

fined region of the falling edge of SCL.

3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL

signal, it must output the next data bit to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specifica-

tion) before the SCL line is released.

Signal

Symbol Reference

Edge

Standard

Mode

Fast

Mode

Unit

Min

Max

Min

Max

I2C(1,4)

SCL

fSCL

none

0

100

0

400

kHz

tHD;STA

4.0

—

0.6

—

s

tR

—

1000

—

300

s

tF

—

300

—

300

s

SDA(2,3)

tSU;DAT

SCL rising

250

—

100

—

s

tHD;DAT

03.450

0.9

s

tR

—

1000

10

300

s

tF

—

300

10

300

s

Start or repeated start

condition

tSU;STA

SDA falling

4.7

—

0.6

—

s

tSU;STO

4.0

—

0.6

—

s

Stop condition

tSU;STO

SDA rising

4.0

—

0.6

—

s

Bus free time between

a stop and start condi-

tion

tBUF

4.7

—

1.3

—

s

Capacitive load for

each bus line

Cb

—

400

—

400

pF