CD4076BMS

FN3325 Rev 0.00

Page 6 of 9

December 1992

FIGURE 1. CD4076BMS LOGIC DIAGRAM

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

 -0.5V

OSCILLATOR

50kHz

25kHz

Static Burn-In 1 Note 1

3 - 6

1, 2, 7 - 15

16

Static Burn-In 2 Note 1

3 - 6

8

1, 2, 7, 9 -16

Dynamic Burn-In Note 1

-

1, 2, 8 - 10, 15

16

3 - 6

7

11 - 14

Irradiation (Note 2)

3 - 6

8

1, 2, 7, 9 - 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K

 5%, VDD = 18V  0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V  0.5V

D

CL

R

Q

Q

D

CL

R

Q

Q

D

CL

R

Q

Q

D

CL

R

Q

Q

OUTPUT

DISABLE

DATA

INPUT

DISABLE

M

N

G1

G2

DATA

1

*

*

*

*

*

DATA

2

*

CLOCK

*

1

2

14

9

10

13

7

12

11

15

DATA

3

*

DATA

4

*

RESET

16

VDD

3Q1

4Q2

5Q3

6Q4

8VSS

VDD

VSS

* ALL INPUTS PROTECTED BY

CMOS PROTECTION NETWORK

*