CD4076BMS

FN3325 Rev 0.00

Page 4 of 9

December 1992

Input Voltage Low

VIL

VDD = 10V, VOH > 9V, VOL <

1V

1, 2

+25oC, +125oC,

-55oC

-3

V

Input Voltage High

VIH

VDD = 10V, VOH > 9V, VOL <

1V

1, 2

+25oC, +125oC,

-55oC

7-

V

Propagation Delay

Clock to Q Output

TPHL1

TPLH1

VDD = 10V

1, 2, 3

+25oC

-

250

ns

VDD = 15V

1, 2, 3

+25oC

-

180

ns

Propagation Delay

Reset

TPHL2

VDD = 5V

1, 2, 3

+25oC

-

460

ns

VDD = 10V

1, 2, 3

+25oC

-

200

ns

VDD = 15V

1, 2, 3

+25oC

-

150

ns

Propagation Delay

3 - State

TPHZ

TPLZ

VDD = 5V

1, 2, 4

+25oC

-

300

ns

VDD = 10V

1, 2, 4

+25oC

-

150

ns

VDD = 15V

1, 2, 4

+25oC

-

120

ns

Propagation Delay

3 - State

TPZH

TPZL

VDD = 5V

1, 2, 4

+25oC

-

300

ns

VDD = 10V

1, 2, 4

+25oC

-

150

ns

VDD = 15V

1, 2, 4

+25oC

-

120

ns

Transition Time

TTHL

TTLH

VDD = 10V

1, 2, 3

+25oC

-

100

ns

VDD = 15V

1, 2, 3

+25oC

-

80

ns

Transition Time

TTLH

VDD = 10V

1, 2, 3

+25oC-

-

ns

VDD = 15V

1, 2, 3

+25oC-

-

ns

Maximum Clock Input

Frequency

FCL

VDD = 5V

1, 2, 3

+25oC3

-

MHz

VDD = 10V

1, 2, 3

+25oC6

-

MHz

VDD = 15V

1, 2, 3

+25oC8

-

MHz

Minimum Data Setup

Time

TS

VDD = 5V

1, 2, 3

+25oC

-

200

ns

VDD = 10V

1, 2, 3

+25oC

-

80

ns

VDD = 15V

1, 2, 3

+25oC

-

60

ns

Minimum Data Hold Time

Reset Pulse Width

TW

VDD = 5V

1, 2, 3

+25oC

-

120

ns

VDD = 10V

1, 2, 3

+25oC

-

50

ns

VDD = 15V

1, 2, 3

+25oC

-

40

ns

Minimum Clock Pulse

Width

TW

VDD = 5V

1, 2, 3

+25oC

-

200

ns

VDD = 10V

1, 2, 3

+25oC

-

100

ns

VDD = 15V

1, 2, 3

+25oC

-

80

ns

Minimum Data Input Set-

Up Time

TS

VDD = 5V

1, 2, 3

+25oC

-

180

ns

VDD = 10V

1, 2, 3

+25oC

-

100

ns

VDD = 15V

1, 2, 3

+25oC

-

70

ns

Maximum Clock Input

Rise and Fall Time

TRCL

TFCL

VDD = 5V

1, 2, 3, 5

+25oC-

15

s

VDD = 10V

1, 2, 3, 5

+25oC-

5

s

VDD = 15V

1, 2, 3, 5

+25oC-

5

s

Input Capacitance

CIN

Any Input

1, 2

+25oC-

7.5

pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on

initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.

5. If more than one unit is cascaded, TRCL should be made less than or equal to the sum of the transition time and the fixed propagation

delay of the output of the driving stage for the estimated capacitive load.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

(Continued)

PARAMETER

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

LIMITS

UNITS

MIN

MAX