FN3321 Rev 0.00

Page 1 of 8

December 1992

FN3321

Rev 0.00

December 1992

CD4069UBMS

CMOS Hex Inverter

DATASHEET

Pinout

CD4069UBMS

TOP VIEW

Functional Diagram

A

G = A

B

H = B

C

I = C

VSS

VDD

F

L = F

E

K = E

D

J = D

1

2

3

4

5

6

7

14

13

12

11

10

9

8

VSS = 7

VDD = 14

A

12

G = A

F

13

12

L = F

B

34

H = B

C

56

I = C

D

98

J = D

E

11

10

K = E

Features

• High Voltage Types (20V Rating)

• Standardized Symmetrical Output Characteristics

• Medium Speed Operation: tPHL, tPLH = 30ns (typ) at

10V

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1

A at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25oC

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Logic Inversion

• Pulse Shaping

• Oscillators

• High-Input-Impedance Amplifiers

Description

CD4069UBMS types consist of six CMOS inverter circuits.

These devices are intended for all general-purpose inverter

applications where the medium-power TTL-drive and logic-

level conversion capabilities of circuits such as the CD4009

and CD4049 Hex Inverter/Buffers are not required.

The CD4069UBMS is supplied in these 14 lead outline pack-

ages:

Braze Seal DIP

H4H

Frit Seal DIP

H1B

Ceramic Flatpack

H3W

Schematic Diagram

FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTERS

VDD

VSS

G = A

G

2(4, 6, 8, 10, 12)

A

1(3, 5, 9, 11, 13)

VDD