AT45DB321E datasheet(9/69 Pages) RENESAS

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AT45DB321E

8784M–DFLASH–02/2022

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of

data. Unlike the Continuous Array Read command, when the end of a page in main memory is reached, the device will

continue reading back at the beginning of the same page rather than the beginning of the next page.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum

SCK frequency allowable for the Main Memory Page Read is defined by the fSCK specification. The Main Memory Page

Read bypasses both data buffers and leaves the contents of the buffers unchanged.

5.7

Buffer Read

The SRAM data buffers can be accessed independently from the main memory array, and utilizing the Buffer Read

command allows data to be sequentially read directly from either one of the buffers. Four opcodes, D4h or D1h for Buffer

1 and D6h or D3h for Buffer 2, can be used for the Buffer Read command. The use of each opcode depends on the

maximum SCK frequency that will be used to read data from the buffers. The D4h and D6h opcode can be used at any

SCK frequency up to the maximum specified by f

CAR1 while the D1h and D3h opcode can be used for lower frequency

read operations up to the maximum specified by f

CAR2.

To perform a Buffer Read using the standard DataFlash buffer size (528 bytes), the opcode must be clocked into the

device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (BFA9 - BFA0). To

perform a Buffer Read using the binary buffer size (512 bytes), the opcode must be clocked into the device followed by

three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0). Following the address

bytes, one dummy byte must be clocked into the device to initialize the read operation if using opcodes D4h or D6h. The

CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte (if using opcodes D4h or

D6h), and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning

of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO).

Program and Erase Commands

6.1

Buffer Write

Utilizing the Buffer Write command allows data clocked in from the SI pin to be written directly into either one of the

SRAM data buffers.

To load data into a buffer using the standard DataFlash buffer size (528 bytes), an opcode of 84h for Buffer 1 or 87h for

Buffer 2 must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer

address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte in the buffer to be written.

To load data into a buffer using the binary buffer size (512 bytes), an opcode of 84h for Buffer 1 or 87h for Buffer 2, must

be clocked into the device followed by 15 dummy bits and nine buffer address bits (BFA8 - BFA0). The nine buffer

address bits specify the first byte in the buffer to be written.

After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If

the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to

be loaded into the buffer until a low-to-high transition is detected on the CS pin.

6.2

Buffer to Main Memory Page Program with Built-In Erase

The Buffer to Main Memory Page Program with Built-In Erase command allows data that is stored in one of the SRAM

buffers to be written into an erased or programmed page in the main memory array. It is not necessary to pre-erase the

page in main memory to be written because this command will automatically erase the selected page prior to the

program cycle.

To perform a Buffer to Main Memory Page Program with Built-In Erase using the standard DataFlash page size

(528 bytes), an opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address

bytes comprised of one dummy bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to be

written, and 10 dummy bits.

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