Table 8. SPI interface timing specification

Parameter

Symbol

Min.

Max.

Unit

Notes

Operating frequency

Fspi

—

20

MHz

MCLK

Time from NCS active and MCLK

falling edge

Tncs_to_clk

0

—

ns

Rise/Fall time on MISO

TriseFallMiso

—

3

ns

With 20 pF load

max

Duty cycle

Duty

40

60

%

Time from MOSI stable to MCLK

rising edge

Tmosi_to_clk

16

—

ns

Time MOSI must remain stable

after MCLK rising edge

Tclk_to_ncs

16

—

ns

Time from last MCLK rising edge

to NCS going inactive

Tclk_to_dat

0

—

ns

Propagation delay from falling

MCLK edge to MISO data valid

—

20

ns

With 20 pF load

max

4.1

SPI write messages

The write timing sequence is shown in Figure 17. SPI writing timing sequence. Once the NCS selects the device,

the master sends a write command to the VL53L8CX. The master then provides a clock to output the status.

The writing sequence starts with the MOSI initial value equal to 1. The address is sent first, and the data is sent

afterwards. The most significant bit is sent first (big-endian format). The address length is 15 bits. Data length is

8 bits.

Figure 17. SPI writing timing sequence

If the host continues to transmit data beyond the first 8 data bits, then the slave goes into auto-increment write

mode. The auto-increment write timing sequence is shown in Figure 18. SPI auto-increment write sequence. The

MOSI initial value is 1. The address is incremented automatically and internally by the slave. Subsequent data

bits correspond to incrementing addresses.

Figure 18. SPI auto-increment write sequence

VL53L8CX

SPI write messages

DS14161 - Rev 2

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