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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STPM066S датащи(PDF) 28 Page - STMicroelectronics |
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STPM066S датащи(HTML) 28 Page - STMicroelectronics |
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28 / 67 page  Figure 18. Timing diagram Table 11. DI, CLK and CSN timing Symbol Parameter Test condition Min. Typ. Max. Unit tCLK Clock period – 1000 – – ns tCLKH Clock high time – 400 – – ns tCLKL Clock low time – 400 – – ns tset CSN CSN setup time, CSN low before rising edge of CLK – 500 – – ns tset CLK CLK setup time, CLK high before rising edge of CSN – 500 – – ns tset DI DI setup time – 25 – – ns thold DI DI hold time – 25 – – ns tr in Rise time of input signal – – – 25 ns DI, CLK, CSN tf in Fall time of input signal – – – 25 ns DI, CLK, CSN Table 12. Output DO Symbol Parameter Test condition Min. Typ. Max. Unit VDOL Output low level IDO = -4 mA – – 0.3 V IDOLK Open Drain leakage current When DO output=high -5 – 5 µA CDO Open Drain input capacitance Guaranteed by design – 10 15 pF STPM066S SPI format and register mapping DS12976 - Rev 2 page 28/67 |
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