STPM066S datasheet(20/67 Pages) STMICROELECTRONICS

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4.2.9

Configurable watchdog and reset

During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle. When

the device is in ACTIVE mode, which means the power up phase has been correctly performed and RESET_B

signal has been released, the watchdog is started with a timeout (long open window TLW ) to allow the

microcontroller to run its own setup and then to start the window watchdog by setting an inner signal TRIG =

1. Subsequently, the micro controller has to serve the watchdog by providing the watchdog trigger bit TRIG within

the safe trigger area TSW. The trigger time is configurable by SPI. A correct watchdog trigger signal immediately

starts the next cycle. A wrong watchdog trigger causes a watchdog failure.

WDI signal can be ignored (by setting OTP bit) and SPI can be used as watchdog: in this case, a specific SPI

right time, a watchdog failure happens. In case of a watchdog failure, a RESET_B is always asserted, and the

device goes to REC mode or keeps in ACTIVE mode depending on the WD_REC_en OTP configuration.

If OTP_WD_REC_en = 1 the device goes to REC mode in case of WD failure, and WD is no more active until the

ACTIVE mode is reached.

If OTP_WD_REC_en = 0, the device keeps in ACTIVE mode in case of WD failure, and WD is inactive for 280 ns

(1 system clock cycle, not significant), then active again in Long open window, and RESET_B asserts a small

pulse (typ 8 µs). Moving SPI_WD_REC_en = 1, the device behavior is the same as OTP_WD_REC_en = 1.

Configuration with OTP_WD_REC_en = 0 is useful if voltages should be immediately active in order to initialize

the system, regardless of the WD signal.

The following picture illustrates the watchdog behavior.

Figure 8. Watchdog behavior

Trig=1

Proper trigger in

window mode

WD is working when in ACTIVE mode and OTP bit is enabled

Window

mode

WD off

Long

open

window

WD is stop

WD is working

Shutdown mode

GAPG2306150737PS

The watchdog trigger time is configured by setting SPI. The change of this time is not limited to the Long Open

Window. It can be changed also in "Window mode" state. However, it is suggested to write these bits only during

the long window, in order to avoid watchdog failures. Besides, the first trigger time should be < TLW (160 ms),

after that, next trigger should happen between (previous _Trigger_ time + TSW_min) and (previous _Trigger_ time

+ TSW_max).

STPM066S

Voltage regulators and features description

DS12976 - Rev 2

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