STPM066S datasheet(46/67 Pages) STMICROELECTRONICS

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6.6

ACTIVE mode

In ACTIVE Mode the regulators are ON and the device is controlled by SPI: SPI communication is active only in

this state. All the regulators, except the Buck regulator and the ones disabled via OTP (ENx = 0), can be turned

on and off via SPI; if the device goes out from ACTIVE mode, OTP power up phase is recovered.

If a fault occurs, the device can stay in ACTIVE Mode or move to REC, depending on the regulator involved and

the kind of fault.

•

A fault that asserts RESET_B moves the IC to the REC phase. WD failure asserting RESET_B depends on

OTP bit WD_REC_en: if WD_REC_en=1, STPM066S moves to REC phase;

•

if WD_REC_en=0, STPM066S keeps in ACTIVE mode.

WKUP pin is continuously monitored: if the signal goes low after a filtering time, then STPM066S goes back to

STANDBY state after proper Power Down phase.

When the IC is switched on for the first time, supplying VBAT1 and/or VBAT2, a fault is asserted by VBAT1_uv or

VBAT2_uv. That’s not a real fault, and it can be cleared by an SPI read&clear command.

6.7

OTP program mode

STPM066S needs a programming phase of OTP (One Time Programmable) cells before starting any operation:

this is allowed by providing battery line higher than 17 V (~20 V) at VBAT1 pin, together with a dedicated SPI

word.

STPM066S is programmed has shown in Section 6.8 OTP bit mapping and register configuration

6.8

OTP bit mapping and register configuration

Figure 22. OTP bit mapping

2 1 0

OTP_WD_REC_en OvRst EN

EnLDO EnBOOST

BOOST CFG

EnVREF

CRC

OTP prg Flag

CRC

SeqId LDO

USR Area Protection

Reset activation

Device identification

BUCK CFG

LDO CFG

PowrOn Delay

VREF CFG

CRC

WDG CFG

SeqId VREF

SeqId BOOST

GADG0306190948PS

Table 14. Reset activation OTP

Bit Nb

Name

Description

Row 8

Bit15:13 Reset_activation<2:0>

(1)

Reset release

000: Reset release after PGOOD of the BUCK with a delay set by PowrOn Delay

001: Reset release after PGOOD of the 2nd regulator with a delay set by PowrOn Delay

010: Reset release after PGOOD of the 3rd regulator with a delay set by PowrOn Delay

011: Reset release after PGOOD of the 4th regulator with a delay set by PowrOn Delay

111: Reset release when ACTIVE state is reached (unconditional Reset release)

1. All regulators switched on before the Reset is released are considered part of the "Reset activation list"

Table 15. Device identification OTP

Bit Nb

Name

Description

Row 8

Bit12:7

Device_id<5:0>

Custom information. It can be read out by SPI.

STPM066S

ACTIVE mode

DS12976 - Rev 2

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