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UPD301A/KYX датащи(PDF) 12 Page - Microchip Technology

номер детали UPD301A/KYX
подробное описание детали  Stand-alone USB Type-C™ Power Delivery 3.0 Controller
PDF  40 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

UPD301A/KYX датащи(HTML) 12 Page - Microchip Technology

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UPD301A
DS00002838B-page 12
 2018-2019 Microchip Technology Inc.
Port Control
PRT_CTRL/OCS
I/O2/OD2 When the UPD301A is in the Source Role, any external
VBUS/VCONN/temperature faults may be wire-ORed on
OCS to indicate a default has occurred, prompting the
device’s firmware to make VBUS safe (open load switches,
discharge VBUS, and enter error recovery).
When the UPD301A is in the Source Role, this pin is a bi-
directional signal indicating various faults to a load switch,
DC/DC converter, DFP or hub. This pin is nominally config-
ured as an output, sending faults to a load switch or DC/DC
converter. However, if a different fault condition (e.g. over-
voltage) is detected internally by the UPD301A, this pin is
reconfigured as an open-drain output with an internal pull-
down enabled and asserted low for a duration to allow
detection by the hub’s PRT_ENx/OCSx_N input, and is
then reconfigured back to an input.
Note:
For proper operation, a 100kOhm pull-up to
+3.3V should be applied to this pin externally.
Type-C
Orientation
ORIENTATION_N
O2
This signal is used to indicate which CC pin is terminated
by the attached device. When asserted CC = CC1, other-
wise CC=CC2.
Note:
For proper operation, a 200kOhm pull-up to
+3.3V should be applied to this pin externally.
System Reset
Input
RESET_N_IN
I
Active low system reset input. This reset is used for reset of
the UPD301A by a companion MCU.
System Reset
Output
RESET_N_OUT
O2
Active low system reset output. This pin must be connected
to RESET_N_COM for proper operation.
System Reset
Common
RESET_N_COM
IS
This pin must be connected to RESET_N_OUT for proper
operation.
No Connect
NC
-
For proper operation, this pin must be left unconnected.
Configuration Straps
Power Delivery
Power Select 0
Configuration
Strap
PDP_SEL0
I/O2
This multi-level configuration strap is sampled after system
reset to specify a Power Delivery Power (PDP) which
defines the voltages and currents to be used by the
UPD301A Power Delivery Objects (PDOs).
Refer to Section 3.3, "Configuration Straps" for additional
information.
Power Delivery
Power Select 1
Configuration
Strap
PDP_SEL1
I/O2
For a two port system, this multi-level configuration strap is
sampled after a system reset to specify a Power Delivery
Power (PDP) which defines the voltages and currents to be
used by the optional external UPD350 Power Delivery
Objects (PDOs).
Refer to Section 3.3, "Configuration Straps" for additional
information.
I2C Address
Select
Configuration
Strap
I2C_ADDR_SEL
AIO
This multi-level configuration signal is sampled after a sys-
tem reset to select the device’s default I2C slave address.
Refer to Section 3.3, "Configuration Straps" for additional
information.
TABLE 3-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Description



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