UPD301A

DS00002838B-page 30

 2018-2019 Microchip Technology Inc.

5.6.2

SPI TIMING

Figure 5-3 and Figure 5-4 illustrate the SPI master and slave timing requirements, respectively. Refer to Section 4.1,

"Serial Peripheral Interface (SPI)" for additional information.

FIGURE 5-3:

SPI MASTER TIMING

FIGURE 5-4:

SPI SLAVE TIMING

SPI_SS

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

SPI_MISO

(Data Input )

SPI_MOSI

(Data Output )

SPI_SS

SPI_CLK

(CPOL = 0)

SPI_CLK

(CPOL = 1)

SPI_MOSI

(Data Input )

SPI_MISO

(Data Output )