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3.7.4 Short Circuit Tolerance

The PFM operation of the DCDC converters along with the programmable peak current limit provide some inherent protection against

an output short circuit. In the buck or buck/boost configuration, any output short condition will result in that DCDC output dropping out of

regulation, with a maximum output current that is approximately IPK_BASE/2 (where IPK_BASE is defined for for DCDC A in

3.2.1.2 Peak Current Configuration and DCDC B in 3.2.2.2 Peak Current Configuration).

Similarly, LDO C and LDO B under an output short condition are limited to the configured maximum output current (as defined in

3.2.3.3 Maximum Output Current).

Note: Depending on the converter programming, an output short circuit condition for either the DCDC or the LDO output current may

still result in an unacceptable rise in on-die temperature. To minimize on-die temperature rise, the PCB designer should maximize ther-

mal connections from the package to the PCB ground planes to optimize heat flow from the package and minimize the θJA.

Note: There is no inherent output short circuit protection for DCDC A when it is configured in wired boost mode as described in the

4.1.5 Wired Boost Configuration (EFP0109 & EFP0110), 4.1.4 Single-Cell Boost Configuration (EFP0108), or 4.1.6 Boost Bootstrap

Configuration (EFP0111). Shorting the VOA output to ground in one of these configurations will result in an uncontrolled battery dis-

charge through the body diode in the boost powertrain PFET. The current, in this case, is limited only by the system impedances, such

as the internal body diode resistance, the inductor resistance, and the battery internal resistance. Any desired short circuit protection for

wired boost modes must be implemented in external circuitry.

Firmware can detect and manage an output short condition through the following mechanisms:

• An output short should cause the output to drop out of regulation, resulting in the corresponding VOx_ISLOW flag being set in the

STATUS_V register.

• In the worst case, where the output short current has resulted in excessive on-chip power dissapation, the TEMP_FAULT flag in the

STATUS_G register will be set to indicate an over temperature condition.

It is recommended that firmware unmask these bits in the STATUS_VM and STATUS_GM registers at start-up so that they can gener-

ate interrupt requests. Firmware can then respond appropriately to the VOx_ISLOW and/or TEMP_FAULT condition(s), e.g. by lowering

the peak current or LDOx_IGAIN setting, increasing the inrush current limit, or disabling the output altogether.

3.8 Startup & Shutdown Behavior

3.8.1 Startup Behavior

Once enabled, the EFP01's DCDC and LDO outputs will immediately begin switching to ramp up to the target output voltage without

any soft-start mechanisms (besides the current limit, if enabled, for DCDC A or DCDC B).

3.8.2 Shutdown Behavior

The outputs of all disabled DCDCs and LDOs are held in a high-impedance state. Note that if an output was first enabled, and then

disabled, the original output voltage may be retained by the output capacitor(s) for a long period of time depending on output load cur-

rent.

When the DCDC A converter is disabled on devices configured for the Wired Boost, Single-Cell Boost, or Boost Bootstrap configura-

tions, the body diode in the boost powertrain becomes forward-biased once the VOA output voltage drops below the battery voltage. In

these configurations, the VOA output (less a diode drop) tracks the battery voltage when DCDC A is disabled.

EFP01 Energy Friendly PMIC Family Data Sheet

System Overview

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