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ST72334J2T3 датащи(PDF) 116 Page - STMicroelectronics |
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ST72334J2T3 датащи(HTML) 116 Page - STMicroelectronics |
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116 / 125 page ![]() ST72334J/N, ST72314J/N, ST72124J 116/125 MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Notes: 1) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide- lines and are not tested. 2) Data based on characterization results, not tested in production. 3) Tested in production at TA=25°C, characterized over the whole temperature range. 4) ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB for each 10K Ω increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input -at 5V VDD supply, and worst case temperature. ADC Analog to Digital Converter (8-bit) Symbol Parameter Conditions Min Typ 1) Max Unit fADC Analog control frequency VDD=VDDA=5V 4 2) MHz |TUE| Total unadjusted error 4) TA=25°C,VDD=VDDA=5V, 3) fCPU=8MHz,fADC=4MHz 1 LSB OE Offset error 4) -0.5 0.5 GE Gain Error 4) -0.5 0.5 |DLE| Differential linearity error 4) 0.5 |ILE| Integral linearity error 4) 0.5 VAIN Conversion range voltage VSSA VDDA V IADC A/D conversion supply current fCPU=8MHz, fADC=4MHz VDD=VDDA=5V 1mA tSTAB Stabilization time after ADC enable 1 µs tLOAD Sample capacitor loading time 1 4 µs 1/fADC tCONV Hold conversion time 2 8 µs 1/fADC RAIN External input resistor 15 2) k Ω RADC Internal input resistor 1.5 k Ω CSAMPLE Sample capacitor 6 pF OE GE 1 LSB (ideal) 1LS B i deal V DDA V SSA – 256 ---------------------------------------- - = Vin (LSBideal) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line TUE=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. OE=Offset Error: deviation between the first actual transition and the first ideal one. GE=Gain Error: deviation between the last ideal transition and the last actual one. DLE=Differential Linearity Error: maximum devia- tion between actual steps and the ideal one. ILE=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Digital Result ADCDR 255 254 253 5 4 3 2 1 0 7 6 12 34 567 253 254 255 256 (1) (2) TUE DLE ILE (3) VDDA VSSA |
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