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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72334J2T3 датащи(PDF) 64 Page - STMicroelectronics |
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ST72334J2T3 датащи(HTML) 64 Page - STMicroelectronics |
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64 / 125 page  ST72334J/N, ST72314J/N, ST72124J 64/125 16-BIT TIMER (Cont’d) 6.4.4 Low Power Modes 6.4.5 Interrupts Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAP i pin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF i bit is set, and the counter value present when exiting from HALT mode is captured into the IC iR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No |
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