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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72334J2T3 датащи(PDF) 34 Page - STMicroelectronics |
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ST72334J2T3 датащи(HTML) 34 Page - STMicroelectronics |
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34 / 125 page  ST72334J/N, ST72314J/N, ST72124J 34/125 4.5 MAIN CLOCK CONTROLLER (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows to man- age the power saving modes such as the SLOW and ACTIVE-HALT modes. The whole functionali- ty is managed by the Main Clock Control/Status Register (MCCSR) and the Miscellaneous Regis- ter 1 (MISCR1). The MCC block consists of: – a programmable CPU clock prescaler – a time base counter with interrupt capability – a clock-out signal to supply external devices The prescaler allows to select the main clock fre- quency and is controlled with three bits of the MISCR1: CP1, CP0 and SMS. The counter allows to generate an interrupt based on a accurate real time clock. Four different time bases depending directly on fOSC are available. The whole functionality is controlled by four bits of the MCCSR register: TB1, TB0, OIE and OIF. The clock-out capability allows to configure a ded- icated I/O port pin as an fOSC/2 clock out to drive external devices. It is controlled by the MCO bit in the MISCR1 register. When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. Figure 25. Main Clock Controller (MCC) Block Diagram DIV 2, 4, 8, 16 MCC INTERRUPT DIV 2 SMS CP1 CP0 TB1 TB0 OIE OIF CPU CLOCK MISCR1 PROGRAMMABLE DIVIDER TO CPU AND PERIPHER ALS fOSC fCPU MCO PORT FUNCTION ALTERNATE OSC2 OSC1 MCO - - - - 0 0 0 0 MCCSR OSCILLATOR MCC fOSC/2 |
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