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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM85C30-8PC датащи(PDF) 67 Page - Advanced Micro Devices |
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AM85C30-8PC датащи(HTML) 67 Page - Advanced Micro Devices |
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67 / 68 page  A M E N D M E N T AMD 14 Am85C30 Unit SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24) 27 TdA(DR) Address Required Valid to Read 220 160 100 90 ns Data Valid Delay 28 TwWRI WR Low Width 150 125 75 65 ns 29 TdWRf(DW) WR ↓ to Write Data Valid 35 35 20 20 ns 30 ThDW(WR) Write Data to WR ↑ Hold Time 0000 ns 31 TdWR(W) WR ↓ to Wait Valid Delay (Note 2) 170 100 50 50 ns 32 TdRD(W) RD ↓ to Wait Valid Delay (Note 2) 170 100 50 50 ns 33 TdWRf(REQ) WR ↓ to W/REQ Not Valid Delay 170 120 70 65 ns 34 TdRDf(REQ) RD ↓ to W/REQ Not Valid Delay 170 120 70 65 ns 35a TdWRr(REQ) WR ↓ to DTR/REQ Not Valid Delay 4TcPc 4TcPc 4TcPc 4TcPc ns 35b TdWRr(EREQ) WR ↓ to DTR/REQ Not Valid Delay 120 120 70 65 ns 36 TdRDr(REQ) RD ↑ to DTR/REQ Not Valid Delay NA NA NA NA ns 37 TdPC(INT) PCLK ↓ to INT Valid Delay (Note 2) 500 400 175 160 ns 38 TdIAi(RD) INTACK to RD ↓ (Acknowledge) 150 125 50 45 ns Delay (Note 3) 39 TwRDA RD (Acknowledge) Width 150 125 75 65 ns 40 TdRDA(DR) RD ↓ (Acknowledge) to Read 140 120 70 60 ns Data Valid Delay 41 TsIEI(RDA) IEI to RD ↓ (Acknowledge) Setup 95 80 50 45 ns Time 42 ThIEI(RDA) IEI to RD ↑ (Acknowledge) Hold 0000 ns Time 43 TdIEI(IEO) IEI to IEO Delay Time 95 80 45 40 ns 44 TdPC(IEO) PCLK ↑ to IEO Delay 200 175 80 70 ns 45 TdRDA(INT) RD ↓ to INT Inactive Delay (Note 2) 450 320 200 180 ns 46 TdRD(WRQ) RD ↑ to WR ↓ Delay for No Reset 15 15 10 10 ns 47 TdWRQ(RD) WR ↑ to RD ↓ Delay for No Reset 15 15 10 10 ns 48 TwRES WR and RD Coincident Low for 150 100 75 65 ns Reset 49 Trc Valid Access Recovery Time 3.5 3.5 3.5 3.5 (Note 1) Notes: 1 Parameter applies only between transactions involving the ESCC, if WR/RD falling edge is synchronized to PCLK falling edge, then TrC = 3TcPc. 2. Open-drain output, measured with open-drain test load. 3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO) for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating them in the daisy chain. 4. Parameter applies to Enhanced Request mode only. No. Parameter Symbol Parameter Description 10 MHz 20 MHz Min Max Min Max 8.192 MHz Min Max Min Max 16.384 MHz Industrial Only TcPc |
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