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AM85C30-8PC датащи(PDF) 49 Page - Advanced Micro Devices

номер детали AM85C30-8PC
подробное описание детали  Enhanced Serial Communications Controller
PDF  68 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM85C30-8PC датащи(HTML) 49 Page - Advanced Micro Devices

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AMD
49
Am85C30
1
TwPCI
PCLK Low Width
50
1000
40
1000
26
1000
ns
2
TwPCh
PCLK High Width
50
1000
40
1000
26
1000
ns
3
TfPC
PCLK Fall Time
15
12
8
ns
4
TrPC
PCLK Rise Time
15
12
8
ns
5
TcPC
PCLK Cycle Time
122
2000
100
2000
61
2000
ns
6
TsA(WR)
Address to
WR
↓ Setup Time
70
50
35
ns
7
ThA(WR)
Address to
WR
↑ Hold Time
0
0
0
ns
8
TsA(RD)
Address to
RD
↓ Setup Time
70
50
35
ns
9
ThA(RD)
Address to
RD
↑ Hold Time
0
0
0
ns
10
TsIA(PC)
I
NTACK to PCLK
↑ Setup Time
20
20
15
ns
11
TsIA(WR)
INTACK to WR
↓ Setup Time
145
120
70
ns
(Note 1)
12
ThIA(WR)
INTACK to WR
↑ Hold Time
0
0
0
ns
13
TsIA(RD)
INTACK to RD
↓ Setup Time
145
120
70
ns
(Note 1)
14
ThIAi(RD)
INTACK to RD
↑ Hold Time
0
0
0
ns
15
ThIA(PC)
INTACK to PCLK
↑ Hold Time
40
30
15
ns
16
TsCEI(WR)
CE Low to WR
↓ Setup Time
0
0
0
ns
17
ThCE(WR)
CE to WR
↑ Hold Time
0
0
0
ns
18
TsCEh(WR)
CE High to WR
↓ Setup Time
60
50
30
ns
19
TsCEI(RD)
CE Low to RD
↓ Setup Time
0
0
0
ns
(Note 1)
20
ThCE(RD)
CE to RD
↑ Hold Time (Note1)
0
0
0
ns
21
TsCEh(RD)
CE High to RD
↓ Setup Time
60
50
30
ns
(Note 1)
22
TwRDI
RD Low Width (Note 1)
150
125
75
ns
23
TdRD(DRA)
RD
↓ to Read Data Active Delay
0
0
0
ns
24
TdRDr(DR)
RD
↑ to Read Data Not Valid Delay
0
0
0
ns
25
TdRDf(DR)
RD
↓ to Read Data Valid Delay
140
125
70
ns
26
TdRD(DRz)
RD
↑ to Read Data Float Delay
40
35
20
ns
(Note 2)
Notes:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and
minimum AC load.
No.
Parameter
Symbol
Parameter
Description
10 MHz
16.384 MHz
Min
Max
Min
Max
Unit
8.192 MHz
Min
Max
SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued)
Read and Write Timing (see Figure 21)



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