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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM85C30-8PC датащи(PDF) 39 Page - Advanced Micro Devices |
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AM85C30-8PC датащи(HTML) 39 Page - Advanced Micro Devices |
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39 / 68 page  AMD 39 Am85C30 1 TdPC(REQ) PCLK ↓ to W/REQ Valid Delay 250 150 80 ns 2 TdPC(W) PCLK ↓ to Wait Inactive Delay 350 250 180 ns 3 TsRXC(PC) RxC ↑ to PCLK ↑ Setup Time NA NA NA NA NA NA (Notes 1, 4 & 8) 4 TsRXD(RXCr) RxD to RxC ↑ Setup Time 0 0 0 ns (Xl Mode) (Note 1) 5 ThRXD(RXCr) RxD to RxC ↑ Hold Time 150 125 50 ns (Xl Mode) (Note 1) 6 TsRXD(RXCf) RxD to RxC ↓ Setup Time 0 0 0 ns (Xl Mode) (Notes 1, 5) 7 ThRXD(RXCf) RxD to RxC ↓ Hold Time 150 125 50 ns (Xl Mode) (Notes 1, 5) 8 TsSY(RXC) SYNC to RxC ↑ Setup Time –200 –150 –100 ns (Note 1) 9 ThSY(RXC) SYNC to RxC ↑ Hold Time 5TcPC 5TcPC 5TcPc ns (Note 1) 10 TsTXC(PC) TxC ↓ to PCLK ↑ Setup Time NA NA NA (Notes 2, 4 & 8) 11 TdTXCf(TXD) TxC ↓ to TxD Delay (Xl Mode) 200 150 80 ns (Note 2) 12 TdTXCr(TXD) TxC ↑ to TxD Delay (Xl Mode) 200 150 80 ns (Notes 2, 5) 13 TdTXD(TRX) TxD to TRxC Delay 200 140 80 ns (Send Clock Echo) 14a TwRTXh RTxC High Width (Note 6) 150 120 80 ns 14b TwRTxh(E) RTxC High Width (Note 9) 50 40 15.6 ns 15a TwRTXI RTxC Low Width (Note 6) 150 120 80 ns 15b TwRTXl(E) RTxC Low Width (Note 9) 50 40 15.6 ns 16a TcRTX RTxC Cycle Time (Notes 6, 7) 488 400 244 ns 16b TcRTx(E) RTxC Cycle Time (Note 9) 125 100 31.25 ns 17 TcRTXX Crystal Oscillator Period (Note 3) 125 1000 100 1000 62 1000 ns 18 TwTRXh TRxC High Width (Note 6) 150 120 80 ns 19 TwTRXI TRxC Low Width (Note 6) 150 120 80 ns 20 TcTRX TRxC Cycle Time (Notes 6, 7) 488 400 244 ns 21 TwEXT DCD or CTS Pulse Width 200 120 70 ns 22 TwSY SYNC Pulse Width 200 120 70 ns SWITCHING CHARACTERISTICS over COMMERCIAL operating range General Timing (see Figure 19) Notes: 1. RxC is RTxC or TRxC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30-pF capacitors to ground connected to them. 4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and PCLK or TxC and PCLK is required. 5. Parameter applies only to FM encoding/decoding. 6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. 7. The maximum receive or transmit data is 1/4 PCLK. 8. External PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation. TRxC and RTxC rise and fall times are identical to PCLK. Reference timing specs Tfpc and Trpc. Tx and Rx input clock slow rates should be kept to a maximum of 30 ns. All parameters related to input CLK edges should be referenced at the point at which the transition begins or ends, whichever is the worst case. 9. ENHANCED FEATURE— RTxC used as input to internal DPLL only. No. Parameter Symbol Parameter Description 10 MHz 16.384 MHz Min Max Min Max Unit 8.192 MHz Min Max |
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