EM6682TP8B datasheet(9/61 Pages) EMMICRO

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EM6682

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4.2 Input Port A Reset

By writing the PA[3/4]ResIn in RegFreqRst registers the PA[3] or PA[4] input becomes dedicated for external reset. This bit is

cleared by POR only. Which input is selected is set by IrqPA[3l/4h] bit from RegPACntl2 register which is described in

Chapter

94H94H

Bit InResAH in the RegFreqRst register selects the PA[3/4] reset function in Active and standby (Halt) mode. If set to ‘0’ the

PA[3/4] reset is inhibited. If Set to ‘1’ than PA[3/4] input goes through a debouncer and needs to respect timing associated

with the debounce clock selection made by DebSel bit in RegPresc register.

This InResetAH bit has no action in sleep mode, where a Hi pulse on PA[3/4] always immediately triggers a system reset.

Overview of control bits and possible reset from PA[3] or PA[4] is specified in table 4.2.1 below.

Table 4.2.1 Possible Reset from PA[3] or PA[4]

PA[3/4]ResIn

InResAH

ACTIVE or STAND-BY mode

SLEEP mode

NO reset from PA[3] or PA[4]

Reset with small analog filter

Debounce reset with debck of

* Ck[14]/ Ck[11]/ Ck[8] needing

0.25 ms / 2 ms / 16ms Hi pulse typ.

Reset with small analog filter

* Ck[14]/ Ck[11]/ Ck[8] are explained in chapter

95H95H

5.2 Prescaler.

4.3 Digital Watchdog Timer Reset

The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will generate

a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by activating an inhibit digital

watchdog bit (NoWDtim) located in RegVLDCntl. At power up, and after any system reset, the watchdog timer is

activated.

If for any reason the CPU stops or stays in a loop where watchdog timer is not periodically cleared, it activates the system

reset signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the watchdog

timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a system reset signal is

generated.

The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and timer

operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer also operates in

standby mode and thus, to avoid a system reset, standby should not be active for more than 2.5 seconds.

From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog timer is

influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It is therefore

recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every second.

It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the counting

sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’, {WDVal1 WDVal0}). When reaching the ‘11’ state, the

watchdog reset will be active within ½ second. The watchdog reset activates the system reset which in turn resets the

watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’.

Table 4.3.1 Watchdog timer register RegSysCntl2

Bit

Name

Reset

R/W

Description

WDReset

Reset the Watchdog (The Read value is always '0')

Resets the Logic Watchdog

no action

SleepEn

R/W

See Operating modes (sleep)

WDVal1

Watchdog timer data 1/4 ck[1]

WDVal0

Watchdog timer data 1/2 ck[1]

PORstatus

1 P*

Power-On-Reset status

1 P* POR sets the PORstatus bit which is cleared by writing register RegSysCntl1

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