LM5145 datasheet(23/70 Pages) TI

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DCR

OUT(CL)

1 s

(s)

1 s R

˜ ¨

(11)

Choose the CCS capacitance greater than or equal to 0.1 μF to maintain a low-impedance sensing network, thus

reducing the susceptibility of noise pickup from the switch node. Carefully observe Section 9.4.1 to make sure

that noise and DC errors do not corrupt the current sense signals applied between the ISNS+ and VOUT pins.

8.3.13 Hiccup Mode Current Limiting

The LM5148 includes an internal hiccup-mode protection function. After an overload is detected, 512 cycles

of cycle-by-cycle current limiting occurs. The 512-cycle counter is reset if four consecutive switching cycles

occur without exceeding the current limit threshold. After the 512-cycle counter has expired, the internal soft

start is pulled low, the HO and LO driver outputs are disabled, and the 16384 counter is enabled. After the

counter reaches 16384, the internal soft start is enabled and the output restarts. The hiccup-mode current limit is

disabled during soft start until the FB voltage exceeds 0.4 V.

8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)

The LM5148 contains gate drivers and an associated high-side level shifter to drive the external N-channel

power MOSFETs. The high-side gate driver works in conjunction with an internal bootstrap diode DBOOT

and bootstrap capacitor CBOOT. During the conduction interval of the low-side MOSFET, the SW voltage is

approximately 0 V and CBOOT charges from VCC through the internal DBOOT. TI recommends a 0.1-μF ceramic

capacitor connected with short traces between the CBOOT and SW pins.

The LO and HO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and

LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn

on, the adaptive dead-time logic first disables HO and waits for the HO voltage to drop below 2 V typical. LO is

allowed to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed until the

LO voltage has dropped below 2 V. This technique ensures adequate dead-time for any size N-channel power

MOSFET implementations, including parallel MOSFET configurations.

Caution is advised when adding series gate resistors, as this can impact the effective dead-time. The selected

high-side MOSFET determines the appropriate bootstrap capacitance value CBOOT in accordance with Equation

12.

BOOT

CBOOT

(12)

where

• QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.

• ΔVCBOOT is the voltage variation of the high-side MOSFET driver after turn-on.

To determine CBOOT, choose ΔVCBOOT such that the available gate drive voltage is not significantly impacted.

An acceptable range of ΔVCBOOT is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic

capacitor, typically 0.1 µF. Use high-side and low-side MOSFETs with logic-level gate threshold voltages.

8.3.15 Output Configurations (CNFG)

The LM5148 can be configured as a primary controller (interleaved mode) or as a secondary controller for

paralleling the outputs for high-current applications with a resistor RCNFG. This resistor also configures if spread

spectrum is enabled or disabled. See Table 8-2. After the VCC voltage is above 3.3 V (typical), the CNFG pin

voltage is monitored and latched. To change the configuration mode, the LM5148 must be powered down, and

VCC must drop below 3.3 V. Figure 8-6 shows the configuration timing diagram.

When the LM5148 is configured as a primary controller with spread spectrum enabled (RCNFG of 41.2 kΩ or 71.5

kΩ), the LM5148 cannot be synchronized to an external clock.

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LM5148

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