FAM65V05DF1

www.onsemi.com

5

ABSOLUTE MAXIMUM RATINGS (TJ = 25°C, unless otherwise specified)

Symbol

Parameter

Conditions

Rating

Unit

INVERTER PART

VPN

Supply Voltage

Applied between P− NU, NV, NW

500

V

VPN(Surge)

Supply Voltage (Surge)

Applied between P− NU, NV, NW

dI/dt ≤ 3 A/ns

575

V

VCES

Collector−Emitter Voltage

at the IGBT/Diode

TJ = 25°C

650

V

±IC

IGBT Continuous Collector

Current

TC = 100°C, TJmax = 175°C (Note 1)

50

A

±ICP

IGBT Peak Collector Pulse

Current

TC = 100°C, TJmax = 175°C,

VCC = VBS = 15 V, less than 1 ms (Note 6)

150

A

PC

Collector Dissipation

TC = 25°C per IGBT

333

W

TJ

Junction Temperature

IGBT/Diode

−40 ~ +175

°C

Driver IC

−40 ~ +150

°C

CONTROL PART

VCC

Control Supply Voltage

Applied between VCC(H), VCC(L) − COM

20

V

VBS

High−side Control Bias Voltage Applied between VB(U) − VS(U),

VB(V) − VS(V), VB(W) − VS(W)

20

V

VIN

Input Signal Voltage

Applied between IN(UH), IN(VH), IN(WH),

IN(UL), IN(VL), IN(WL) − COM

−0.3 ~ VCC + 0.3

V

VFO

Fault Output Supply Voltage

Applied between VFO − COM

−0.3 ~ VCC + 0.3

V

IFO

Fault Output Current

Sink Current at VFO Pin

5

mA

VSC

Current Sensing Input Voltage

Applied between CSC − COM

−0.3 ~ VCC + 0.3

V

VTS

Temperature Sense Unit

−0.3 ~ 2/3 × VCC

V

TOTAL SYSTEM

TSTG

Storage Temperature

−40 ~ 125

°C

VISO

Isolation Voltage

60 Hz, Sinusoidal, AC 1 minute,

Connection Pins to heat sink plate

2500

Vrms

TLEAD

Max Lead Temperature at the

Base of the Package During

pcb Assembly

No remelt of internal solder joints

200

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

PACKAGE CHARACTERISTICS

Symbol

Parameter

Conditions

Typ

Max

Unit

Rth(j−c)Q

Junction to Case Thermal

Resistance (Note 2)

Inverter IGBT part (per IGBT)

−

0.45

°C/W

Rth(j−c)F

Inverter FWD part (per DIODE)

−

0.85

°C/W

Ls

Package Stray Inductance

P to NU, NV, NW (Note 3)

24

−

nH

1. Current limited by package terminal, defined by design.

2. Case temperature measured below the package at the chip center, compliant with MIL STD 883−1012.1 (single chip heating), DBC

discoloration allowed, please refer to application note AN−9190 (Impact of DBC Oxidation on SPM Module Performance).

3. Stray inductance per phase measured per IEC 60747−15.