LPC55S2X datasheet(56/140 Pages) NXP

56 / 140 page

LPC55S2x/LPC552x

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Product data sheet

Rev. 2.2 — 8 December 2022

56 of 139

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

7.23.1.1 USB0 device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory. The serial

interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

• USB2.0 full-speed device controller supporting crystal-less operation in device mode

using software library example in technical note (TN00063).

• Supports ten physical (five logical) endpoints including one control endpoint.

• Single and double-buffering supported.

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

• Supports wake-up from Deep-sleep mode on USB activity and remote wake-up.

• Supports SoftConnect.

• Link Power Management (LPM) supported.

7.23.1.2 USB0 host controller

The host controller enables full- and low-speed data exchange with USB devices attached

to the bus. It consists of register interface, serial interface engine and DMA controller. The

Features

• OHCI compliant.

• Two downstream ports.

7.23.2 High-Speed USB Host/Device Interface (USB1)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

7.23.2.1 USB1 device controller

The device controller enables 480 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer memory. The serial

interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

• Fully compliant with USB 2.0 Specification (high speed).

• Supports 12 physical (6 logical) endpoints with up to 8 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

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