LPC55S2X datasheet(43/140 Pages) NXP

43 / 140 page

LPC55S2x/LPC552x

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Product data sheet

Rev. 2.2 — 8 December 2022

43 of 139

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M33

The NVIC is an integral part of the Cortex-M33. The tight coupling to the CPU allows for

low interrupt latency and efficient processing of late arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

• 60 vectored interrupts.

• Eight programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table using Vector Table Offset Register (VTOR).

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.6 System Tick timer (SysTick)

The ARM Cortex-M33 core include a system tick timer (SysTick) that is intended to

generate a dedicated SYSTICK exception. The clock source for the SysTick can be the

system clock or the SYSTICK clock.

7.7 On-chip static RAM

The LPC55S2x/LPC552x support up to 256 KB SRAM with separate bus master access

for higher throughput and individual power control for low-power operation.

7.8 On-chip flash

The LPC55S2x/LPC552x supports up to 512 kB of on-chip flash memory.

7.9 On-chip ROM

The on-chip ROM contains the bootloader and the following features:

• Booting of images from on-chip flash.

• Supports CRC32 image integrity checking.

• Supports flash programming through In System Programming (ISP) commands over

following interfaces: USB0/1 interfaces using HID Class device, UART interface

(Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9) using mode 3

(CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)

• ROM API functions: Flash programming API, Power control API, and Secure firmware

update API using NXP Secure Boot file format, version 2.0 (SB2 files).

• Supports booting of images from PRINCE encrypted flash region.

• Supports NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1

(RSA-4096)

• Supports setting a sealed part to Fault Analysis mode through Debug authentication.

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