TLP5231

10

11.2.

11.2.

11.2.

11.2. Switching Characteristics (Note)

Switching Characteristics (Note)

Switching Characteristics (Note)

Switching Characteristics (Note)

(Unless otherwise specified, T

(Unless otherwise specified, T

(Unless otherwise specified, T

(Unless otherwise specified, Taaaa = -40 to 110

= -40 to 110

= -40 to 110

= -40 to 110 





, V

, V

, V

, VCC2

CC2

CC2

CC2

- V

- V

- V

- VE

E

E

E

= 15 V, V

= 15 V, V

= 15 V, V

= 15 V, VE

E

E

E

- V

- V

- V

- VEE

EE

EE

EE

= 8 V)

= 8 V)

= 8 V)

= 8 V)

Characteristics

Propagation delay time

from DESAT threshold to

50% of high VGMOS

Propagation delay time

from DESAT threshold to

50% of high VOUTP

Propagation delay time

from DESAT threshold to

50% of high VFAULT

Propagation delay time

from 50% VGMOS to 50%

of VOUTN

DESAT Mute time

DESAT leading edge

blanking time

DESAT filter time

High-level common-mode

transient immunity

Low-level common-mode

transient immunity

Symbol

t1

t2

t3

t4

tMUTE

tDESAT

(LEB)

tDESAT

(FILTER)

CMH

CML

Note

(Note 1)

(Note 2)

(Note 3)

(Note 4)

(Note 5)

(Note 6)

Test

Circuit

Fig.13.1.18

Fig.13.1.19,

Fig.13.1.21

Fig.13.1.20,

Fig.13.1.22

Test Condition

CP = CN = 4 nF, CG = 1 nF,

f = 100 Hz, duty = 50 %,

IF = 8 mA, CBLANK = 200 pF,

VDESAT = 8.0 V

RF = 10 kΩ, CF = 1 nF,

VCC1 = 3.3 or 5 V, f = 100 Hz,

duty = 50 %, IF = 8 mA

CP = CN = 4 nF, CG = 1 nF,

f = 100 Hz, duty = 50 %,

IF = 8 mA

IF = 8 mA



RDESAT = 100 Ω, Vin = 10 V,

PW = 1 µs,

monitor: VOUTP, VGMOS

Ta = 25 , |VCM| = 1500 Vp-p,

VCC1 = 5 V (IF = 0 mA),

Rin = 220 Ω (with split resistors)

Ta = 25 , |VCM| = 1500 Vp-p,

VCC1 = 5 V (IF = 8 mA),

Rin = 220 Ω (with split resistors)

Min









0.68





±25

±25

Typ.

450

380

8

45

1.1

580

290





Max

750

700

20



1.7









Unit

ns

µs

ns

ms

ns

kV/µs

Note:

All typical values are at Ta = 25 .

CG means the external MOSFET gate capacitance for soft gate turn-off.

Note 1: Input signal duty = 50 %, tr = tf = 5 ns or less

Note 2: Automatic reset time from protected operation.If the input voltage of a DESAT pin exceeds VDESAT, VOUTP

moves to high level, VOUTN set to low level, VGMOS moves to high level and FAULT moves to high level, then

protected operation will start. If a gate input signal returns to a low level, automatic reset of the protected

operation will be carried out after tMUTE. Refer to Fig. 13.2.2 and Fig. 13.2.3.

Note 3: Disabling time for incorrect detection prevention in case a gate control signal inputs.Refer to Fig. 13.2.2.

Note 4: Disabling time for incorrect detection prevention when the input voltage to a DESAT pin exceeds VDESAT.

( tDESAT(FILTER) < t1, t2 )

Note 5: CMH is the maximum rate of fall of the common mode voltage that can sustained with the output voltage in the

logic high state (VOUTP - VE > 12 V, VOUTN - VEE > 5 V or VFAULT > 2 V).

Note 6: CML is the maximum rate of rise of the common mode voltage that can sustained with the output voltage in

the logic low state (VOUTP - VE < 1 V, VOUTN - VEE < 1 V or VFAULT < 0.8 V).

2020-03-02

Rev.2.0

©2019-2020

Toshiba Electronic Devices & Storage Corporation