TLP5231

4

7.

7.

7.

7. Absolute Maximum Ratings (Note) (Unless otherwise specified, T

Absolute Maximum Ratings (Note) (Unless otherwise specified, T

Absolute Maximum Ratings (Note) (Unless otherwise specified, T

Absolute Maximum Ratings (Note) (Unless otherwise specified, Taaaa = 25

= 25

= 25

= 25 





))))

LED

(controller

side)

Detector

(gate

driver

side)

Common

Characteristics

Input forward current

Input forward current derating

Peak transient input forward

current

Peak transient input forward

current derating

Input reverse voltage

Positive input supply voltage

FAULT output current

FAULT terminal voltage

Input power dissipation

Input power dissipation

derating

Peak high-level output current

Peak low-level output current

Total output supply voltage

Negative output supply voltage

Positive output supply voltage

High side output voltage

Low side output voltage

DESAT voltage

VGMOS voltage

Output power dissipation

Output power dissipation

derating

Operating temperature

Storage temperature

Lead soldering temperature

Isolation voltage

(Ta ≥ 95 )

(Ta ≥ 95 )

(Ta ≥ 95 )

(Ta = -40 to 110 )

(Ta = -40 to 110 )

(Ta ≥ 95 )

(10 s)

(AC, 60 s, R.H. ≤ 60 %)

Symbol

IF

∆IF/∆Ta

IFPT

∆IFPT/∆Ta

VR

VCC1

IFAULT

VFAULT

PD

∆PD/∆Ta

IOPH

IOPL

(VCC2-VEE)

(VE-VEE)

(VCC2-VE)

VOUTP(Peak)

VOUTN(Peak)

VDESAT

VGMOS

PO

∆PO/∆Ta

Topr

Tstg

Tsol

BVS

Note

(Note 1)

(Note 2)

(Note 2)

(Note 3)

(Note 3)

(Note 4)

(Note 4)

(Note 4)

(Note 2)

(Note 5)

(Note 6)

Rating

25

-0.84

1

-34

5

-0.5 to 7

8

-0.5 to VCC1

150

-5.0

-2.5

+2.5

-0.5 to 35

-0.5 to 17

-0.5 to 30

VE - 0.5 to VCC2 + 0.5

VEE - 0.5 to VE + 0.5

VE - 0.5 to VCC2 + 0.5

VEE - 0.5 to VE + 0.5

410

-14.0

-40 to 110

-55 to 125

260

5000

Unit

mA

mA/

A

mA/

V

V

mA

V

mW

mW/

A

A

V

V

V

V

V

V

V

mW

mW/







Vrms

Note:

Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the

significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even

if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum

ratings.

Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook

("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test

report and estimated failure rate, etc).

Note 1: Pulse width (PW) ≤ 1µs, 300pps

Note 2: Mounting on the substrate made in accordance with JEDEC JESD51-7.

Note 3: Exponential waveform. Pulse width ≤ 0.2 µs, f ≤ 15 kHz, VCC2 = 15 V

Note 4: Positive and Negative power supply (VCC2/VEE) must be used in the gate drive circuit.

Note 5: ≥ 2 mm below seating plane.

Note 6: This device is considered as a two-terminal device: Pins 1 through 8 are shorted together, and pins 9 through

16 are shorted together.

2020-03-02

Rev.2.0

©2019-2020

Toshiba Electronic Devices & Storage Corporation