GS816272CC datasheet(27/31 Pages) GSI

27 / 31 page

GS816272CC-333/300/250/200/150

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 2/2005

27/31

JTAG Port Timing Diagram

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

VIHJ3

2.0

VDD3 +0.3

3.3 V Test Port Input Low Voltage

VILJ3

–0.3

0.8

2.5 V Test Port Input High Voltage

VIHJ2

0.6 * VDD2

VDD2 +0.3

2.5 V Test Port Input Low Voltage

VILJ2

–0.3

0.3 * VDD2

TMS, TCK and TDI Input Leakage Current

IINHJ

–300

TMS, TCK and TDI Input Leakage Current

IINLJ

–1

100

TDO Output Leakage Current

IOLJ

–11

Test Port Output High Voltage

VOHJ

1.7

—

V5, 6

Test Port Output Low Voltage

VOLJ

—

0.4

5, 7

Test Port Output CMOS High

VOHJC

VDDQ – 100 mV

—

V5, 8

Test Port Output CMOS Low

VOLJC

—

100 mV

5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V

≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOLJC = +100 uA

tTH

tTS

tTKQ

tTH

tTS

tTH

tTS

tTKL

tTKH

tTKC

TCK

TDI

TMS

TDO

Parallel SRAM input

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