GS816272CC-333/300/250/200/150

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 2/2005

26/31

© 2004, GSI Technology

JTAG TAP Instruction Set Summary

Instruction

Code

Description

Notes

EXTEST

000

Places the Boundary Scan Register between TDI and TDO.

1

IDCODE

001

Preloads ID Register and places it between TDI and TDO.

1, 2

SAMPLE-Z

010

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

Forces all RAM output drivers to High-Z.

1

RFU

011

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

SAMPLE/

PRELOAD

100

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

1

GSI

101

GSI private instruction.

1

RFU

110

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

1

BYPASS

111

Places Bypass Register between TDI and TDO.

1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

Output reference level

DQ

50

Ω

JTAG Port AC Test Load

* Distributed Test Jig Capacitance