Data Sheet

ADRF5144

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 11 of 12

The ADRF5144 has two power supply pins (VDD and VSS) and

one control pin (CTRL). Figure 15 shows the external components

and connections for supply and control pins. The VDD pin and the

VSS pin are decoupled with 100 pF and 10 nF multilayer ceramic

capacitor, while the control pin is decoupled with 100 pF multilayer

ceramic capacitor. The device pin out allows the placement of

the decoupling capacitors close to the device. No other external

components are needed for bias and operation, except DC blocking

capacitors on the RF pins when the RF lines are biased at a voltage

different than 0 V. For more details, see the Pin Configuration and

Function Descriptions section.

Figure 15. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally and the pin out is

designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-

teristic impedance on the PCB. Figure 16 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003 dielectric material. RF trace with 14 mil width and 7 mil

clearance is recommended for 1.5 mil finished copper thickness.

Figure 16. Example PCB Stack Up

Figure 17 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as

many filled, through vias as allowed for optimal RF, and thermal

performance. The primary thermal path for the device is the bottom

side, therefore a heatsink is required underneath the PCB to ensure

maximum heat dissipation and to reduce thermal rise on the PCB

during high-power applications.

Figure 17. PCB Routings

Figure 18 shows the recommended layout from the device RF pins

to the 50 ohm CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn soldermask

defined and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width till the

package edge and tapered to RF trace with 45° angle. The paste

mask is also designed to match the pad without any aperture reduc-

tion. The paste is divided into multiple openings for the paddle.

Figure 18. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, and for further recommendations, contact Analog

Devices, Inc., Technical Support Request.