| поискавой системы для электроныых деталей |
|
AS3682 датащи(PDF) 35 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS3682 датащи(HTML) 35 Page - ams AG |
|
35 / 43 page ![]() AS3682 austriamicrosystems Data Sheet Serial Interface www.austriamicrosystems.com Revision 2.21 35 - 43 In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the ACKNOWL- EDGE bit of the word address transfer. After the reception of the device read address, the slave becomes the transmit- ter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a NOT ACKNOWLEDGE, and issues a STOP condition on the bus. Figure 22. Sequential Read Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsequently transferred. In contrast to the Random Read, in a Sequential Read the transferred register-data bytes are responded to by an ACKNOWLEDGE from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge fol- lowing the last data byte and subsequently generate the STOP condition. Figure 23. Current Address Read To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the first regis- ter byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes must be responded to with an ACKNOWLEDGE from the master. For termination of the transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a subsequent STOP condition. 11.9.4 Fixed ID Register Reading register 15h always returns CDh and can be used to verify the correct operation of the serial interface. Table 36. Fixed ID Register Addr: 15 Fixed_ID This register holds the device ID value. Bit Bit Name Default Access Description 7:0 Device_ID 11001101 R This is the device ID. SDA W A WA A Sr DA R A data 1 A data 2 ... A data n NP WA++ Read Register WA++ S DA R A data 1 A data 2 … A data n NP Read Register WA++ WA++ Read Register WA++ Read Register WA++ Read Register WA++ |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |