8.3 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6 V to 6.5 V. The input supply must

be well regulated and free of spurious noise. To ensure that the LP5912-EP output voltage is well regulated and

dynamic performance is optimum, the input supply must be at least VOUT + 0.5 V. A minimum capacitor value of

1 µF is required to be within 1 cm of the IN pin.

8.4 Layout

8.4.1 Layout Guidelines

The dynamic performance of the LP5912-EP is dependent on the layout of the PCB. PCB layout practices that

are adequate for typical LDOs can degrade the PSRR, noise, or transient performance of the LP5912-EP.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5912-EP, and as

close to the package as practical. The ground connections for CIN and COUT must route back to the LP5912-EP

ground pin using as wide and as short of a copper trace as practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided.

Such connections add parasitic inductances and resistance that result in inferior performance, especially during

transient conditions.

8.4.2 Layout Example

1

2

3

6

5

4

OUT

NC

PG

IN

GND

EN

CIN

RPG

COUT

Thermal Vias (2)

Figure 8-4. LP5912-EP Layout Example

www.ti.com

LP5912-EP

SNVSC57 – SEPTEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

Submit Document Feedback

23

Product Folder Links: LP5912-EP