7.3.3 Reverse Current Protection (IRO)

The LP5912-EP input is protected against reverse current when the output voltage is higher than the input

voltage. In the event that extra output capacitance is used at the output, a power-down transient at the input

normally causes a large reverse current through a conventional regulator. The LP5912-EP includes a reverse

voltage detector that trips when VIN drops below VOUT, shutting off the regulator and opening the p-channel

metal-oxide-semiconductor field effect transistor (PMOS) body diode connection, preventing any reverse current

from the OUT pin from flowing to the IN pin.

If the LP5912-EP EN pin is low (the LP5912-EP is off) and the OUT pin is held high by a secondary supply,

current flows from the secondary supply through the automatic discharge pulldown resistor to ground. This

scenario is not reverse current, but is instead automatic discharge pulldown current.

Reverse current (IRO) is measured at the IN pin.

7.3.4 Internal Current Limit (ISC)

The internal current limit circuit protects the LDO against high-load current faults or shorting events. The LDO

is not designed to operate continuously at the ISC current limit. During a current-limit event, the LDO sources

constant current. Therefore, the output voltage falls when load impedance decreases. If a current limit occurs

and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a

thermal shutdown of the output.

7.3.5 Thermal Overload Protection (TSD)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C, which

allows the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry

enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit

may cycle on and off. This thermal cycling limits the dissipation of the regulator, thus protecting the regulator

from damage as a result of overheating.

7.3.6 Power-Good Output (PG)

The LP5912-EP has a power-good function that works by toggling the state of the PG output pin. When

the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages (low

impedance to GND). When the output voltage rises above the PG threshold voltage (PGVHTH), the PG pin

becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can

receive PG as a logic signal. Make sure that the external pullup supply voltage results in a valid logic signal for

the receiving device or devices. Use a pullup resistor from 10 kΩ to 100 kΩ for best results.

The input supply, VIN, must be no less than the minimum operating voltage of 1.6 V to ensure that the PG pin

output status is valid. The PG pin output status is undefined when VIN is less than 1.6 V.

In the power-good function, the PG output pin being pulled high is typically delayed 140 µs after the output

voltage rises above the PGHTH threshold voltage. If the output voltage rises above the PGHTH threshold and then

falls below the PGLTH threshold voltage, the PG pin falls immediately with no delay time.

If the PG function is not needed, the pullup resistor can be eliminated, and the PG pin can be either connected to

ground or left floating.

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LP5912-EP

SNVSC57 – SEPTEMBER 2022

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