MICRF505BML datasheet(23/27 Pages) MICREL

23 / 27 page

May 13, 2004

M9999-051304

MICRF505

Micrel

When Modulation1 Modulation0 is 10, two sets of divider

values need to be programmed. The formula for calculating

the M,N and A values is given in chapter Frequency synthe-

sizer. The divider values stored in the M0-, N0- and A0-

registers will be used when transmitting a ‘0’ and the M1-, N1-

and A1-registers will be used to transmit a ‘1’. The difference

between the two carrier frequencies corresponds to the

double sided frequency modulation. Opposite from the modu-

lation with the modulator, the PLL shall now lock on a new

frequency for every change in the transmitted data. The PLL

bandwidth therefore needs to be relatively high, higher bit

rate requires a higher PLL bandwidth and vice versa.

The data to be transmitted shall be applied to pin DataIXO

(see chapter Transceiver sync-/non-synchronous mode on

how to use the pin DataClk). The DataIXO pin is set as input

in transmit mode and output in receive mode. When set as

input, a weak voltage divider will set the level to Vdd/2, when

it is not pulled up or down by the controller. When using the

modulator, it is important that the DataIXO is kept tristated

until the transmission shall begin (when PLL is in lock and the

PA is turned on). When DataIXO is tristated, the PLL will lock

on the LO frequency (used in receive mode). When DataIXO

is set either high or low, the RF frequency will be shifted up

or down, centered around the LO-frequency. This is only

important when using the modulator, for the other modulation

method, if DataIXO is tristated, the M0-, N0 and A0 registers

will be used.

Modulator

A6..A0

0000100

Mod_F2

Mod_F1

Mod_F0

Mod_I4

Mod_I3

Mod_I2

Mod_I1

Mod_I0

0000101

—

“0”

“1”

Mod_A3

Mod_A2

Mod_A1

Mod_A0

0000110

—

Mod_clkS2

Mod_clkS1

Mod_clkS0

BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

0000111

BitRate_clkS1 BitRate_clkS0

RefClk_K5

RefClk_K4

RefClk_K3

RefClk_K2

RefClk_K1

RefClk_K0

The modulator will create a waveform with programmable

amplitude and frequency. This waveform is fed into a modu-

lation varactor in the VCO which will create the desired

frequency modulation. The frequency spectrum can be nar-

rowed by increasing the rise- and fall times of the waveform.

The modulator waveform is created by charging and dis-

charging a capacitor. A modulator clock controls the timing,

as shown in Figure 13. For every rise- and fall edge, 4 clock

periods are being used. The charging current during these 4

clock periods are not equal, this is to reduce the high-

frequency components in the waveform, which in turn will

narrow the frequency spectrum.

The frequency deviation can be set in three different ways, as

will be explained below. A formula for setting the desired

deviation is given at the end of this chapter.

Modulator Clock

Modulator Waveform

Figure 15. Modulator Waveform and Clock

Modulator Clock

The modulator clock frequency is set by:

Refclk_K

Mod_clk

XCO

7 Mod_clkS

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where fMOD_CLK is the modulator clock shown in Figure 13,

fXCO is the crystal oscillator frequency, Refclk_K is a 6 bit

number and Mod_clkS is a 3 bit number. Mod_clkS can be set

to a value between 0 and 7. The modulator clock frequency

should be set according to the bit rate and shaping.

Mod_clka

Mod_clkb

Mod_clkb > Mod_clka

Figure 16. Two Different Modulator Clock Settings

A fMOD_CLK of 8 times the bit rate (as in Figure 14) corre-

sponds to a signal filtered in a gaussian filter with a

Bandwidth(Period-product (BT) of 1. When BT is increased,

the waveform will be less filtered. Minimum BT is 1 (Mod_clk

is 8 times the bitrate). Figure 14 shows two waveforms with

BT=1 and BT=2, i.e. the Mod_clk is 8 and 16 times higher than

the bit rate. When changing the BT factor, the charge- and

discharge times will also be changed, and therefore the

frequency deviation, as shown in Figure 15.

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