MICRF505

Micrel

M9999-051304

16

May 13, 2004

Lock Detect

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000001

Modulation1

Modulation0

"0"

"0"

RSSI_en

LD_en

PF_FC1

PF_FC0

A lock detector can be enabled by setting LD_en = 1. When pin LD is high, it indicates that the PLL is in lock.

Modes of Operation

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

Load_en

Mode1 Mode0

State

Comments

0

0

Power down

Keeps register configuration

0

1

Standby

Only crystal oscillator running

1

0

Receive

Full receive

1

1

Transmit

Full transmit ex PA stage

Transceiver Sync/Non-Synchronous Mode

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

Load_en

0000110

–

Mod_clkS2

Mod_clkS1

Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

0000111

BitRate_clkS1 BitRate_clkS0 RefClk_K5

RefClk_K4

RefClk_K3

RefClk_K2

RefClk_K1

RefClk_K0

Sync_en

State

Comments

0

Rx: Bit synchronization off

Transparent reception of data

0

Tx: DataClk pin off

Transparent transmission of data

1

Rx: Bit synchronization on

Bit-clock is generated by transceiver

1

Tx: DataClk pin on

Bit-clock is generated by transceiver

When Sync_en = 1, it will enable the bit synchronizer in

receive mode. The bit synchronizer clock needs to be pro-

grammed, see chapter Bit synchronizer. The synchronized

clock will be set out on pin DataClk.

In transmit mode, when Sync_en = 1, the clock signal on pin

DataClk is a programmed bit rate clock. Now the transceiver

controls the actual bit rate. The data to be transmitted will be

sampled on rising edge of DataClk. The micro controller can

therefore use the negative edge to change the data to be

transmitted. The clock used for this purpose, BitRate-clock,

is programmed in the same way as the modulator clock and

the bit synchronizer clock:

f

f

Refclk_K

2

BITRATE_CLK

XCO

=

¥

-

()

7

BITRATE clkS

_

where:

fBITRATE_CLK: The clock frequency used to

control the bit rate, should be equal to the bit rate (a

bit rate of 20 kbit/sec requires a clock frequency of

20kHz)

fxco: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1 and 63

BitRate_clkS: Bit rate setting, values between 0 and 6