MICRF505BML datasheet(17/27 Pages) MICREL

17 / 27 page

May 13, 2004

M9999-051304

MICRF505

Micrel

Data Interface

The MICRF505 interface can be divided in to two separate

interfaces, a “programming interface” and a “Data interface”.

The “programming interface” has a three wire serial program-

mable interface and is described in chapter Programming.

The “data interface” can be programmed to sync-/non-syn-

chronous mode. In synchronous mode the MICRF505 is

defined as “Master” and provides a data clock that allows

users to utilize low cost micro controller reference frequency.

The data interface is defined in such a way that all user

actions should take place on falling edge and is illustrated

Figure 6 and 7. The two figures illustrate the relationship

between DATACLK and DATAIXO in receive mode and

transmit mode.

MICRF505 will present data on rising edge and the “USER”

sample data on falling edge in receive mode.

DATAIXO

DATACLK

Figure 9. Data interface in Receive Mode

The User presents data on falling edge and MICRF505

samples on rising edge in transmit mode.

DATAIXO

DATACLK

Figure 10. Data interface in Transmit Mode

When entering transmit mode it is important to keep DATAIXO

in tri-state from the time Tx-mode is entered until user starts

sending data. The data is provided directly to the modulation

circuit and violation of this may/will cause abnormal behavior.

Depending on the chosen FSK modulation some sort of

encoding might be needed. The different modulation types

and encoding is described in chapter Frequency modulation.

Receiver

The receiver is a zero intermediate frequency (IF) type in

order to make channel filtering possible with low-power

integrated low-pass filters. The receiver consists of a low

noise amplifier (LNA) that drives a quadrature mixer pair. The

mixer outputs feed two identical signal channels in phase

quadrature. Each channel include a pre-amplifier, a third

order Sallen-Key RC lowpass filter that protects the following

switched-capacitior filter from strong adjacent channel sig-

nals and finally a limiter. The main channel filter is a switched-

capacitor implementation of a six-pole elliptic lowpass filter.

The elliptic filter minimizes the total capacitance required for

a given selectivity and dynamic range. The cut-off frequency

of the Sallen-Key RC filter can be programmed to four

different frequencies: 100kHz, 150kHz, 230kHz and 340kHz.

The demodulator demodulates the I and Q channel outputs

and produces a digital data output. It detects the relative

phase of the I and the Q channel signal. If the I channel signal

lags the Q channel, the FSK tone frequency lies above the LO

frequency (data ‘1’). If the I channel leads the Q channel, the

FSK tone lies below the LO frequency (data ‘0’). The output

of the receiver is available on the DataIXO pin. A RSSI circuit

(receive signal strength indicator) indicates the received

signal level.

Front End

A6..A0

0000011 LNA_by

PA2

PA1

PA0 Sync_en Mode1 Mode0 Load_en

A low noise amplifier in RF receivers is used to boost the

incoming signal prior to the frequency conversion process.

This is important in order to prevent mixer noise from domi-

nating the overall front-end noise performance. The LNA is a

two-stage amplifier and has a nominal gain of approximately

23dB at 900MHz. The front end has a gain of about 33dB to

35dB. The gain varies by 1-1.5dB over a 2.0V to 2.5V

variation in power supply.

The LNA can be bypassed by setting bit LNA_by to ‘1’. This

can be useful for very strong input signal levels. The front-end

gain with the LNA bypassed is about 9-10dB. The mixers

have a gain of about 10dB at 900MHz. The differential

outputs of the mixers can be made available at pins IchOut

and QchOut. The output impedance of each mixer is about

The input impedance is close to 50k

W as shown in Figure 8,

giving an input reflection of about -20dB. The receiver does

not require any matching network.

Figure 11. LNA Input Impedance

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